Effective Chip Area Research Articles

A 2.5–8V input range peak-current-control non-inverting buck-boost DC-DC converter with high efficiency and automatic mode transition for Ni-MH battery application

In portable electronic devices, the output voltage of the Ni-MH cell battery gradually decreases with the extension of run time, eventually leading to an inability to provide the required operating voltage. As a result, this paper proposed a non-inverting buck-boost converter with automatic switching of operating modes to extend the run time of Ni-MH batteries connected in series, which is peak current controlled. By comparing the input and output voltages, the DC-DC converter is placed in either buck, boost, or buck-boost mode. Of the three modes, the buck-boost mode is designed to have the smallest operating range due to its lowest power conversion efficiency. The converter is characterised by a wide input range of 2.5–8 V, which exceeds the maximum voltage leading to oxide breakdown. In order to prevent the breakdown of the gate oxide layer, a capacitive coupling level shift circuit is proposed to control voltage between gate and source of the power transistor below 5 V. The proposed converter is manufactured using a 180 nm BCD process and occupies an effective chip area of 1.44 mm × 0.73 mm. Experimental results demonstrate that the maximum power conversion efficiency of the proposed buck-boost DC-DC converter is 93%, marking a significant 11% enhancement compared to the traditional buck-boost DC-DC converter operating in only buck-boost mode (84% efficient). In addition, the converter achieves a maximum output current of 500 mA, which improves the output maximum current by 67% compared to the traditional DC-DC converter (max. output current 300 mA).

9.9 µW, 140 dB DR, and 93.27 dB SNDR, Double Sampling ΔΣ Modulator Using High Swing Inverter-Based Amplifier for Digital Hearing Aids

In this paper, an ultra-low-power second-order, single-bit discrete-time (DT) double sampling ΔΣ modulator was proposed for hearing aid applications. In portable biomedical devices that are permanently used such as hearing aids, short battery lifetime and power dissipation are considerable issues. In a typical delta–sigma modulator, the most power-consuming parts are the operational transconductance amplifiers (OTAs), and their elimination without loss of efficiency is now challenging. This proposed modulator includes an ultra-low-power self-biased inverter-based amplifier with swing enhancement instead of power-hungry OTAs. Low voltage amplifier design reduces output swing voltage, affecting delta–sigma modulator efficiency and decreasing the signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) values. In this article, the proposed amplifier’s source and tail transistors were biased in the sub-threshold region, increasing the output swing voltage significantly and leading to desired properties for a hearing aid modulator. The proposed amplifier peak-to-peak swing voltage was approximately 1.01 V at a 1 V power supply. In addition, the proposed modulator design used a standard 180 nm CMOS technology, which obtained 140 dB DR and 93.27 dB SNDR for a 10 kHz signal bandwidth with an oversampling ratio (OSR) of 128. Finally, the modulator’s effective chip area was 0.02 mm2 and consumed only about 9.9 µW, while the figure of merit (FOMW) and FOMs achieved 1.31 fJ/step and 183.31, respectively.

Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory

This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock control method are introduced. Besides, the multifunctional charge pump also supports stage control, which can further reduce the power consumption. A wordline voltage generator with this proposed scheme has been fabricated in a 0.18 μm BCD process, and the effective chip area is 2.4mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurement results show that the total power consumption of Incremental Step Pulse Programming (ISPP) is reduced by 18.7% compared with the conventional one. What's more, the maximum peak current is reduced by 35%.

A Tunable SiGe BiCMOS Gain-Equalizer For X-Band Phased-Array RADAR Applications

This brief presents a compact-size tunable gain-equalizer for X-band phased-array RADAR applications in a 0.25- $ \mu \text{m}$ SiGe BiCMOS technology. An isolated nMOS-based variable resistance was used for the first time to tune the slope of the gain-equalizer. For nMOS, an isolated body created by a deep n-well was utilized to reduce insertion loss due to the substrate conductivity. Furthermore, the power-handling capability of the tunable gain-equalizer was improved thanks to the resistive body-floating technique. The designed tunable gain-equalizer operates in the frequency range from 8 to 12.5 GHz with a measured positive slope of 1 dB/GHz and 1 dB tunable slope. The effective chip area excluding the pads is 0.21 mm2, and the total area including pads is 0.31 mm2. To authors best knowledge, this brief is the first tunable gain-equalizer in SiGe technology presented for X-band phased-array RADAR applications.

A Small Ripple Program Voltage Generator Without High-Voltage Regulator for 3D NAND Flash

This brief presents a programmable voltage generator with the scheme of separated dynamic clock voltage scaling for program operation in 3D NAND flash memories, where the ripple of program voltage can be minimized to reduce the variation of threshold voltage of the programmed cells. The proposed scheme drastically reduces the output ripple and improves the loop stability at the same time. What’s more, the high voltage regulator used in the conventional wordline voltage generator is not necessary anymore. The proposed generator has been implemented in a 0.18 $\mu \text{m}$ triple-well CMOS process, and the effective chip area is 0.55 mm2. Under the equivalent load conditions of 3D NAND flash, the measurement results show that the maximum ripple voltage is 2.06 mV, and the ripple is independent from clock frequency and output voltage. Moreover, the peak efficiency is about 36% at 23 V output voltage.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

Self-start-up fully integrated DC-DC step-up converter using body biasing technique for energy harvesting applications

An ultra-low power, self-start-up switched-capacitor Two Branch Charge Pump (TBCP) circuit for low power, low voltage, and battery-less implantable applications is proposed. In order to make feasible the low voltage operation, the proposed charge pump along with Non-Overlapped Clock generator (NOC) are designed working in sub-threshold region by using body biasing technique. A four-stage TBCP circuit is implemented with both NMOS and PMOS transistors to provide a direct load flow. This leads to a significant drop in reverse charge sharing and switching loss and accordingly improves pumping efficiency. A post-layout simulation of designed four-stage TBCP has been performed by using an auxiliary body biasing technique. Consequently, a low start-up voltage of 300 mV with a pumping efficiency of 95% for 1 pF load capacitance is achieved. The output voltage can rise up-to 1.88 V within 40 μs with 0.2% output voltage ripple in case of using 400 mV power supply. The designed circuit is implemented by 180-nm standard CMOS technology with an effective chip area of 130.5 μm × 141.8 μm while the whole circuit consumes just 3.2 μW.

A 93.3% Peak-Efficiency Self-Resonant Hybrid-Switched-Capacitor LED Driver in 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m CMOS Technology

This paper presents an integrated light-emitting diode (LED) driver based on a self-resonant hybrid-switched-capacitor converter (H-SCC) operating in the megahertz range. An integrated zero-current detection (ZCD) circuit is designed to enable self-resonant operation and zero-current switching. A self-resonant timer is proposed to set the switching frequency to resonance automatically, accommodating for variations in the LED voltage, output current, inductor value, and/or parasitic components, and improving the converter efficiency at light loads without the need for an accurate clock with variable frequency. A ZCD threshold control is also proposed to enable continuous conduction mode and improve efficiency at large currents. The design of high-speed integrated current sensors to measure the inductor current in the H-SCC is also presented. Capacitors, power switches, ZCD, current monitors, and the control circuitry of the LED driver are integrated on-chip in a low-cost, 5-V, 0.18- $\mu \text{m}$ bulk CMOS technology. The proposed driver was measured using inductor values between 36 and 470 nH. It achieves a peak efficiency of 93.3% and an efficiency of 83.1% at the nominal current. The LED driver is able to control a 700-mA LED down to less than 10% of its nominal current. The effective chip area is 7.5 mm2, and the maximum power density is 373 mW/mm2. To our knowledge, this LED driver can achieve efficiencies comparable to prior art LED drivers using a 6.6 $\times $ smaller inductor.

A SiGe HBT $D$ -Band LNA With Butterworth Response and Noise Reduction Technique

This letter presents a wideband high-gain four-stage cascode $D$ -band low noise amplifier (LNA) implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. A shunt inductor that is used at the intermediate node of the cascode topology to reduce the noise contribution of the common base transistor is analyzed and employed for the first time for the SiGe HBT technology. Furthermore, the staggered-tuning technique based on the Butterworth distribution is utilized to have a wideband flat-gain characteristic. The designed LNA has a measured 32.6-dB peak gain at 144.5 GHz with a 3-dB bandwidth of 52 GHz. The measured noise figure (NF) is lower than 6.1 dB across the whole $D$ -band, and its minimum value is 4.8 dB. The total dc power consumption is 28 mW. To the authors’ best knowledge, these results demonstrate the lowest NF performance and the widest 3-dB bandwidth among the $D$ -band LNAs implemented in the silicon-based technologies. The effective chip area excluding the pads is 0.6 mm2, and the total IC occupies an area of 1 mm2.

A High Gain, Bulk Driven Operational Transconductance Amplifier (OTA) for Wireless Body Area Networks

This paper presents a bulk driven operational transconductance amplifier (OTA) operating in weak inversion region. The OTA is designed and implemented in 1P-9M Standard UMC 90 nm CMOS Process, and achieves a gain of 94.4 dB and a unity gain bandwidth of 48.97 MHz. Positive feedback, gm boosted, source degeneration is employed at the input of bulk driven differential pair of the amplifier. An NMOS differential pair is used at the output stage to enhance the gain as well as the bandwidth. The OTA consumes power as low as 57 nW. Comparison with the previously reported designs is made on the basis of gain, noise power spectral density and bandwidth. The results show significant improvement in the performance of the proposed OTA as compared to previously reported designs. The effective chip area of this OTA is 0.0147 mm2.

A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter

A new resistorless linear voltage-to-current converter (VCC) utilizing ten MOS transistors is described. The circuit uses saturated MOS transistors with different threshold voltages to produce an output current that is linearly related to the input voltage. The compensation of high-order nonlinear errors is also presented. The VCC has been fabricated using a 0.18- $\mu\mbox{m}$ standard CMOS technology. Measured results show that the proposed VCC achieves nonlinearity of less than ±2.2% in the input voltage range of 1.3–3 V with maximum power consumption of 0.21 mW and effective chip area of 2200 $\mu \mbox{m}^{2}$ .

An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique

An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter with a 45 nm CMOS process is described. In order to improve the non-linearity error of a conventional folding amplifier, a new symmetrical zero-crossing technique is proposed. Further, a digital error correction logic to rectify the distortion errors of analog blocks is also discussed. The proposed chip has been fabricated with 1.2 V 45 nm Samsung CMOS technology. The effective chip area is 1.98 mm2 and the power dissipation is about 80 mW. The measured result of SNDR is about 38 dB, when the input frequency is 1 GHz at the sampling frequency of 2 GS/s. The measured INL is within +2.5 LSB/?2.0 LSB and DNL is within +1.0 LSB/?1.0 LSB.

An approach to the microscopic study of wear mechanisms during hard turning with coated ceramics

The influence of tool edge microgeometry on the wear of tool inserts made from mixed oxide ceramics is investigated. The microgeometry of ceramic inserts is described using quantifiable data, including, tool edge radius (rn), roughness of the rake face (Ra) and tool edge roughness (sometimes called ‘tool edge sharpness’) Rt. Applied coatings affect these quantifiable data. Total force and mean temperature were measured to identify the safe operating region in which the tool edge is not chipped or damaged. The effect of tool microgeometry on wear progress for two types of mixed oxide ceramics-TiN-coated and uncoated, were compared using both macroscopic and microscopic tool wear data. A geometrical approach was used to determine the effective chip area at the chamfered tool edge. This involved mathematical modelling where the effective chip area, effective tool edge length and maximum distance between two subsequent transient surfaces were determined. The total forces were divided into cutting parts and parasitic parts, using both effective chip area and effective tool edge length. Total force division during hard machining operations with uncoated and TiN-coated ceramic inserts, enabled us to compare the effects of tool edge microgeometry on the main mechanisms of wear. Secondary wear areas at the chamfered tool edge were identified for both ceramic types. Hard machining produced abrasive wear pattern and smearing particles due to thermal load for uncoated ceramics; while it produced particles with iron content in the secondary wear area of TiN-coated ceramics.

A CMOS Current-Steering D/A Converter With Full-Swing Output Voltage and a Quaternary Driver

This brief describes a CMOS current-steering digital-to-analog converter (D/A converter, DAC) with a full-swing output signal. Generally, a normal current-steering DAC cannot have a full-swing output signal because conventional DACs have an inevitable voltage drop at the output current cell. In order to improve the drawbacks, we propose a new scheme of quaternary driver and an output current cell composed of both nMOS and pMOS. First, the nMOS operates from the power supply to the half of the power supply. Second, the pMOS operates independently from the half of the power supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. A 6-bit 1-GS/s current-steering DAC has been fabricated with Dongbu 0.11-μm 1-poly 6-metal (1P6M) CMOS technology to verify the performance of the proposed full-swing DAC. The effective chip area is 0.46 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and power consumption is about 19.1 mW. The measured results reveal that the DAC has a full-swing output signal.

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99 mm 2 and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is 2.1 mm 2 (ADC core : 1.4 mm 2 , calibration engine : 0.7

자가보정 바이어스 기법을 이용한 Current Steering 10-bit CMOS D/A 변환기 설계

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

전치 증폭기 공유 기법을 이용한 8-bit 10-MSample/s Folding &amp; Interpolation ADC

본 논문에서는 8bit 10Ms/s CMOS Folding and Interpolation ADC를 제안한다. 회로에 사용한 구조는 FR(Folding Rate)이 3, NFB(Number of Folding Block)가 4, IR(Interpolation rate)이 8이며, 제안된 전치 증폭기(Preamplifier) 공유 기법을 회로에 사용하여 같은 구조에서 요구하는 전치 증폭기 수를 절반으로 줄여서 전력소모와 유효면적을 줄이도록 설계하였다. 제안된 ADC는 0.35[um] CMOS 디지털 공정을 사용하여 제작하였고, 유효칩 면적은 3.8[<TEX>$mm^2$</TEX>] (<TEX>$1.8[mm]{\times}2.11[mm]$</TEX>) 이고, 3.3[V], 샘플링 주파수 10[MHz]에서 20[mA]의 DC 전류소모를 나타내었다. INL은 -0.57, +0.61 [LSB], DNL은 -0.4, +0.51 [LSB]으로 측정되었고, 주파수 100[kHz] 정현파 입력신호에서 SFDR은 48.9[dB], SNDR은 47.9[dB](ENOB 7.6b)로 측정되었다. In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is <TEX>$1.8[mm]{\times}2.11[mm]$</TEX> and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

Design space exploration of thermal-aware many-core systems

Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future 3D IC technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues in 2D and 3D systems, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. In this paper, we propose a thermally efficient routing strategy for 3D NoC-Bus Hybrid architectures, which mitigates on-chip temperatures by conducting most of the switching activity closer to the heat sink. Our simulations with a real world benchmark show that there has been a significant decrease in the peak temperatures when compared to a typical stacked mesh 3D NoC. Also, we have presented an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems. Various thermal models have been developed in order to investigate the effect of thermal-aware placement in 2D chip and 3D stacked systems. Using the developed metrics, we proposed an efficient thermal-aware application mapping for a 2D NoC. Steady-state simulations show that the proposed thermal-aware mapping algorithm reduces the effective chip area reeling under high temperatures when compared to the Tree-Model-Based (TMB) mapping and Worst case mapping.

Multi-Channel Stimulator IC Using a Channel Sharing Method for Retinal Prostheses

A retinal stimulator is an implantable device restoring vision by supplying a controlled, stimulating electrical signal to people blinded by retinal diseases such as age-related macular degeneration (AMD) and retinitis pigmentosa (RP). The resolution requirements of artificial retina systems become increasingly significant in their design as well as their usefulness. At least 32 x 32 pixels are required to provide a minimal visual function. However, a retinal stimulator with a high resolution imposes severe constraints on interface electronics. In this paper, a new stimulator IC (integrated chip) using a channel sharing technique is developed to minimize the circuit size, power consumption, as well as overheating of retina tissues. The proposed current-mode stimulator is fabricated by a 0.35 microm 2-poly/4-metal BCDMOS technology. Attention is given to minimizing the silicon area so that higher channel numbers can be implemented. The stimulator for each channel can provide output current in the range of 0-350 muA. The effective chip area excluding the pads is 1.2 mm x 1.2 mm.