An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique

Abstract

An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter with a 45 nm CMOS process is described. In order to improve the non-linearity error of a conventional folding amplifier, a new symmetrical zero-crossing technique is proposed. Further, a digital error correction logic to rectify the distortion errors of analog blocks is also discussed. The proposed chip has been fabricated with 1.2 V 45 nm Samsung CMOS technology. The effective chip area is 1.98 mm2 and the power dissipation is about 80 mW. The measured result of SNDR is about 38 dB, when the input frequency is 1 GHz at the sampling frequency of 2 GS/s. The measured INL is within +2.5 LSB/?2.0 LSB and DNL is within +1.0 LSB/?1.0 LSB.