A 10-b 500MS/s CMOS cascaded folding A/D converter with a hybrid calibration and a prevision error correction logic

Abstract

In this paper, a 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and a new error correction logic is discussed. The proposed ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. In order to overcome the disadvantage of offset error, at the open-loop amplifier, a hybrid self-calibration circuit is proposed. Further, a novel prevision digital error correction logic (DCL) for folding ADC is also described. The ADC prototype using 130 nm 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is 1.55 mm and the power dissipates 300 mW including peripheral circuits at 1.2/1.5 V power supply.