Power Supply Noise Effects Research Articles

Design and Distortion Analysis of a Power Delivery Network in the Presence of Internal Supply Noise

This article presents a novel relationship between the duty cycle and power supply noise (PSN) for a feedback control circuit of a dc–dc buck converter. The derived relation is equally valid for the other high-speed circuits. Based on the derived relation, the closed-form expressions of the harmonics quantities for the dc–dc buck converter (including feedback circuitry) and power delivery network (PDN) are developed. The derived expressions of the distortions include the effect of small variations at the power supply and input dc terminals. A combination of two techniques, the Volterra series and the estimation-by-inspection methods, are used to derive the nonlinear quantities. The estimation-by-inspection method is used to model the feedback circuit, including the effects of PSN. The Volterra series derive the nonlinear quantities of the converter. The analytical results are compared with the simulation results for both the examples (designed in 180-nm LDMOS technology) in terms of mean percentage error (MPE) and computational (CPU) time.

Phase Noise Analysis of Clock Generator by Using Phase Noise Sensitivity

Phase noise represents signal instabilities in the frequency domain and is assessed through power measurements at various offsets from the carrier frequency. Herein, the phase noise of a clock generator is analyzed and modeled. Sources for the phase noise of the clock output at the resonance frequency are identified, including the power supply, the heat sink, and the external crystal. Low-frequency resonance is detected and validated to be caused by the external crystal grounding design. Solutions to decrease crystal-related noise are proposed and validated. In addition, the sensitivity based on the signal-to-noise ratio is proposed and verified with measurements, to numerically analyze the effects of power supply noise on clock phase noise. The proposed phase noise sensitivity is extracted from the measured phase noise results and can be used to estimate the phase noise and jitter of different power supply noises. The extraction and prediction method are validated with different buffer types including LVDS, HCSL, LVPECL, and LVCMOS in a device under test with the given design.

Modeling and Measurement of Power Supply Noise Effects on an Analog-to-Digital Converter Based on a Chip-PCB Hierarchical Power Distribution Network Analysis

In this paper, a model of power supply noise (PSN) effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) coanalysis and comodeling are required to accurately evaluate the performance of the ADC. We propose the comodel which allows the estimation and analysis of PSN effects on the ADC including off-chip characteristic. The proposed model includes three separate submodels: a power distribution network (PDN) model from the power/ground of the PSN source to the ADC power/ground, an on-chip circuit model from the ADC power/ground to the ADC inputs, and an ADC behavioral model from the ADC inputs to the factor of the effective number of bits (ENOB), which is one of the ADC performance factors. By applying a segmentation method for the PDN model, an analytical model for the on-chip circuit model, and a MATLAB model for the ADC behavioral model, fast, precise, and broadband estimations of the PSN effects are achieved. To validate the proposed models, an ADC was fabricated by a 0.13-μm CMOS process and wire bonded to the designed PCB. The ENOB of the ADC was measured by sweeping the PSN's frequency from 1 MHz up to 3 GHz, which was injected into the PCB to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the cosimulated and measured results. The proposed modeling procedure saves the chip, package, and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect.

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characterization. The proposed test pattern generation flow is a simulated-annealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC'99 benchmarks and show that path delay variation can be considerable if test patterns are not properly selected.

The Correction Method for Power Noise in Digital Class D Power Amplifiers

In a digital class D power amplifier, the distortion is introduced into the input signal being amplified in power stage, due to the effect of power supply noise. A method used to eliminate the distortion is presented in the paper. This method is adding correction factors to all integrators of Delta-Sigma modulator, and introducing power supply noise to the input of the class D power amplifier and Delta-Sigma modulator. A design example with the method is presented, and the simulation results indicate this method can eliminate the error introduced by power stage.

NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test

Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode.

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects

As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure is proposed to maximize PSN effects on critical paths considering the impact of local voltage drop. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed on the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practised in industry.

A second-order PWM-in/PWM-out class-D audio amplifier

Class-D audio amplifiers convert an audio signal into a high-frequency square wave whose switching times are modulated according to that audio signal. Thus, they operate using so-called pulse-width modulation. When the high-frequency components of the output square wave are removed by filtering, the remaining lower frequency components can reproduce the audio signal with very little distortion. This low distortion, coupled to the high efficiency of class-D amplifiers, is responsible for the increasing use of these devices in a wide variety of applications. However, to date there has been very little predictive mathematical modelling of those class-D amplifiers that employ negative feedback, as is usually the case in practice. Here, we derive and investigate a mathematical model for a novel design of the output stage for a class-D audio amplifier, which employs negative feedback to remove the effects of power supply noise on the amplifier's performance.

Bang–Bang Control Class-D Amplifiers: Power-Supply Noise

In this paper, the bang-bang control class-D amplifiers (bang-bang amp) is suggested as an alternative to the incumbent pulsewidth-modulation class-D amp for low voltage power-critical applications, including hearing aids. The effects of power supply noise, qualified by power-supply rejection ratio (PSRR), on two bang-bang amps, bang-bang type-I and type-II, are investigated for low signal bandwidth hearing aid applications and for the usual full audio bandwidth applications. By deriving analytical expressions for PSRR of these amps, the important parameters related to PSRR are analyzed. The analyses are verified by means of HSPICE simulations and by measurements on practical circuits. The relationships derived herein provide good practical insight to the design of bang-bang amps, including how various parameters may be varied/optimized to meet a given PSRR specification.

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI

This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.

Supporting cost-effective innovation

In the nanoscale regime, speed and density of semiconductor technology continue to increase. However, skyrocketing design costs for developing gigascale system chips have slowed the creation of new design projects. Moreover, existing design and test solutions have not addressed increasing variability and reliability concerns. Variability can stem from noise, process variations, thermal effects, and power-related issues. Among these, power-induced variations can wreak havoc on performance verification and delay testing. This issue of D&T examines recent progress in dealing with noise and variations caused by IR-drop and power supply noise effects.

Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs

As technology scales to 22 nm and functional density continues to rise, many factors and parameters have a direct impact on the design and test of chips. Among such challenges, IR-drop and power supply noise (PSN) effects have become more significant in recent years. This special issue addresses some of the key issues in this area, focusing on the impact of PSN on design and test of very deep-submicron designs, and highlighting the importance of PSN and IR drop to design and test engineers in the semiconductor industry and academic researchers.

Timing violations due to <i>V<sub>DD</sub>/V<sub>SS</sub></i> bounce

Abstract. The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

Call for Papers: Special Issue on IR-Drop and Power Supply Noise Effects on Design and Test of Very Deep-Submicron Designs

Call for Papers: Special Issue on IR-Drop and Power Supply Noise Effects on Design and Test of Very Deep-Submicron Designs

Call for Papers: Special Issue on IR-Drop and Power Supply Noise Effects on Design and Test of Very Deep-Submicron Designs

Call for Papers: Special Issue on IR-Drop and Power Supply Noise Effects on Design and Test of Very Deep-Submicron Designs

Noise-Shaping Sense Amplifier for MRAM Cross-Point Arrays

A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (a counter) is presented for use with cross-point MRAM arrays and magnetic tunnel junction memory cells. The presented technique eliminates the need for precision components, the use of calibrations, and reduces the effects of power supply noise. To obviate the effects of cell-to-cell variations in the array, a digital self-referencing scheme using the counter is presented. Measured experimental results in a 180-nm CMOS process indicate an RMS sensing noise of 20 /spl mu/V for a 5-/spl mu/s sense time. Further increases in sense time are shown to increase the signal-to-noise ratio. The current used by the sense amplifier and counter was measured as 10 /spl mu/A when running at 100 MHz or 10 mA when 1000 sense amplifiers are used with a memory subarray having 1000 bitlines.

Trigger uncertainty in period-to-code converters based on counters embedded in microcontrollers

Abstract Microcontrollers with embedded counters offer a simple, compact interface for quasi-digital sensors whose output period depends on the measurand. However, as opposed to bench-top universal counters, manufacturers of microcontrollers do not specify the uncertainty inherent to measurements performed with embedded time-counters. This paper analyses the effects of input signal slew rate, signal-to-noise ratio and power supply noise on the uncertainty of periods measured with a PIC16F873 microcontroller. That uncertainty is evaluated by the standard deviation and histogram of the measured time periods. Two noise parameters have been considered: bandwidth (for Gaussian noise) or frequency (for sinusoidal interference), and intensity (rms amplitude). Trigger uncertainty increases for slow signal slew rate, and it is slightly larger when Gaussian noise or sine wave interference are added to the input signal than when they are added to the power supply. Interference whose frequency is close (but not equal) to that of the input signal yields larger trigger uncertainty than interference whose frequency is apart from that of the input signal. Trigger uncertainty resulting from Gaussian noise of a given rms power increases for reduced noise bandwidth.

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. In this paper, we propose a methodology to capture the effects of these statistical variations on circuit performance. It incorporates statistical information into timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. Next, we propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure. We apply the proposed path selection technique for selection of a set of paths for dynamic timing analysis considering power supply noise effects. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered versus when these effects are ignored. Thus, they indicate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.

Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

Noise effects such as power supply and crosstalk noise can significantly impact the performance of deep submicrometer designs. Existing delay testing and timing analysis techniques cannot capture the effects of noise on the signal/cell delays. Therefore, these techniques cannot capture the worst case timing scenarios and the predicted circuit performance might not reflect the worst case circuit delay. More accurate and efficient timing analysis and delay testing strategies need to be developed to predict and guarantee the performance of deep submicrometer designs. In this paper, we propose a new pattern generation technique for delay testing and dynamic timing analysis that can take into account the impact of the power supply noise on the signal propagation delays. In addition to sensitizing the selected paths, the new patterns also cause high power supply noise on the nodes in these paths. Thus, they also cause longer propagation delays for the nodes along the paths. Our experimental results on benchmark circuits show that the new patterns produce significantly longer delays on the selected paths compared to the patterns derived using existing pattern generation methods.

Power Estimation and Power Noise Analysis for CMOS Circuits

Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.