Effect Of Post-oxidation Annealing Research Articles

Effects of high-temperature diluted-H2 annealing on effective mobility of SiC MOSFETs estimated by split capacitance–voltage technique

The effects of post-oxidation annealing (POA) in diluted-H2 ambient on 4H- and 6H-SiC/SiO2 interfaces were investigated. Effective mobility (μeff) was extracted from lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) by the split capacitance–voltage (C–V) technique to determine the surface charge density and a calibration technique using two MOSFETs with different gate lengths to minimize the contribution of parasitic components. POA at 1150 °C in diluted-H2 ambient resulted in an enhancement of μeff, compared with that in N2 ambient. It was indicated that the effects of POA in diluted-H2 ambient should be attributed to the reduction in the density of near-interface traps in oxide, which disturb the electron transportation in the inversion channel, from the measurement temperature dependence of μeff for 6H-SiC MOSFETs as well as from the C–V curves of MOS capacitors fabricated on n-type 4H-SiC.

Effects of high-temperature diluted-H2 annealing on effective mobility of 4H-SiC MOSFETs with thermally-grown SiO2

The impact of post-oxidation annealing (POA) in diluted-H2 ambient on a 4H-SiC/SiO2 interface was investigated with a cold wall furnace. Effective mobility (μeff) was extracted from lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) by applying the split capacitance–voltage (C–V) technique to the determination of charge density and a calibration technique using two MOSFETs with different gate lengths to minimize the contribution of parasitic components. POA at 1150 °C in diluted-H2 ambient resulted in an enhancement of μeff compared with that for POA in N2 ambient. It was indicated that the effects of POA in diluted H2 should be attributed to the reduction in the density of near interface traps, which disturb the electron transportation in the inversion channel, from the measurement temperature dependence of μeff as well as from the C–V curves of MOS capacitors fabricated on n-type SiC.

Effects of post oxidation annealing on electrical and interface properties of high pressure water vapor oxidized SiO2/SiC metal-oxide-semiconductor capacitors

Oxide has been grown on 4H-SiC samples using a high pressure oxidation system at temperature as low as 400 and 450°C using water vapor. Effect of post oxidation annealing (POA) in various ambient on electrical and structural properties of this oxide has been systematically investigated. X-ray photoelectron spectroscopy with sputter depth profile has been carried out to study the incorporation of nitrogen in the oxide. Significant nitrogen incorporation has been observed at the SiO2/SiC interface with POA in O2+N2 ambient resulting in effective passivation of the SiO2/SiC interface. This is reflected in the low interface state density and leakage current as well as high breakdown field strength for the samples with POA in O2+N2 compared to those for the sample with POA in N2. A very small hysteresis window (<10mV) also indicates low charge trapping and a good SiO2/SiC interface for the samples with POA in O2+N2.

Effect of Post-Oxidation Annealing in Wet O&lt;sub&gt;2&lt;/sub&gt; and N&lt;sub&gt;2&lt;/sub&gt;O Ambient on Thermally Grown SiO&lt;sub&gt;2&lt;/sub&gt;/4H-SiC Interface for P-Channel MOS Devices

We investigated the effect of post-oxidation annealing in wet O2 and N2O ambient, following dry O2 oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO2/SiC interface, in each POA process. Notably, the N2O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O2-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.

Effect of post oxidation annealing on electrical characteristics of Ni/SiO2/4H-SiC capacitor with varying oxide thickness

This paper describes an experimental observation of post oxidation annealing (POA) treatment on current-voltage and capacitance-voltage characteristics of Ni/SiO2/4H-SiC system with varying oxide thickness. The leakage current of fabricated structures shows an asymmetric behavior having noticeable effect of POA with the polarity of gate bias (+V or −V at the anode). When compared with the conventional wet oxidation, the POA processes greatly reduce interface-state density and enhance reliability of devices. An extensive increment in the barrier height at SiO2/4H-SiC interface was observed due to POA, which resulted into lower forward leakage current. A significant improvement in the oxide charges are also demonstrated using C-V characteristics of POA treated structures.

Effect of Ar post-oxidation annealing on oxide–4H-SiC interfaces studied by capacitance to voltage measurements and photoemission spectroscopy

The effect of post-oxidation annealing in Ar atmosphere (Ar POA) on 4H-SiC–oxide interfaces has been studied by capacitance to gate-bias voltage (C–V) measurements and photoemission spectroscopy (PES). It was found from the C–V measurements that the shift of the C–V curve disappears when the Ar POA temperature is higher than 600 °C. On the other hand, angle-resolved x-ray photoelectron spectroscopy measurements revealed that the thickness of the intermediate layers containing Si1+ oxidation states observed at the interfaces decreases abruptly when the Ar POA temperature exceeds 500 °C. In ultraviolet photoelectron spectra, O2p peaks were changed by Ar POA at temperatures higher than 600 °C, which is the temperature where the shift of the C–V curve disappears in C–V measurements. This shows that the change in O2p bonding by Ar POA is the origin of the shift observed in C–V characteristics. A model of structural changes in the interfaces by Ar POA has been proposed based on the results of PES measurements and those of C–V measurements.

Photoemission Spectroscopic Studies on Oxide/SiC Interfaces Formed by Dry and Pyrogenic Oxidation

The difference in the structure of oxide/SiC interface between dry and pyrogenic oxidation and the effect of post-oxidation annealing in Ar atmosphere on the interfaces have been studied by X-ray and ultraviolet photoelectron spectroscopy to make clear the interface structures which spoil the electrical properties. It is found that intermediate layers containing Si 1+ oxidation states exist in both cases of oxidation method and the thickness of the layer changes by Ar annealing. It is also found that the oxide/SiC band offsets and the structures of O2p peak, observed in valence band spectra, change remarkably by Ar POA in both cases of oxidation method. The bond states at SiC/oxide interfaces have been discussed by considering these results together with the results from C-V measurements.

Effect of post-oxidationannealing on the electrical properties of deposited oxide andoxynitride films on strained-Si0.82Ge0.18 layers

Silicon dioxide and oxynitride films have been deposited on strained-Si0.82Ge0.18 layers at a low temperature using tetraethylorthosilicate (TEOS), TEOS/O2 and TEOS/NO plasma. Effect of post-oxidation annealing (POA) time (at 700 °C) on theelectrical properties of the dielectrics have been studied. The border trap (Qbt) generation has been characterized usingthe hysteresis in high-frequency capacitance-voltage (C-V) characteristics.It has been observed that the interface trap charge density (Dit) and gate voltage shift (ΔVG) decrease with POA time. Under Fowler-Nordheim constant current stressing, the charge trapping behaviour and the amount of border trap charge density are found to be low in the case of TEOS/NO-plasma-deposited oxynitride films compared with TEOS- and TEOS/O2-plasma-deposited oxide films.

Effect of Post-oxidation Annealing on GaAs Oxides Grown by Liquid Phase Chemical-Enhanced Technique

The characteristics of GaAs native oxides grown by liquid phase chemical-enhanced oxidation technique followed by post-oxidation annealing are investigated. The refractive index of as-grown oxide films increases with increasing As/Ga ratio, which depends on many process factors such as temperature, oxidizing time and pH values of the aqueous solution. Regardless of high or low refractive index as-grown oxide films, their refractive index approaches 1.8 after post-oxidation annealing. A model is proposed to explain this observation. Crystalline β-Ga2O3 is present in the oxide when the oxide is annealed at temperatures above 600°C and when the annealing time exceeds 6h. The shrinkage of oxide film thickness has been found. 30% enhancement of breakdown field strength and an order of magnitude of reduction of leakage current have been also obtained.

Effect of Postoxidation Annealing on Si / SiO2 Interface Roughness

We use a plan‐view transmission electron microscope technique to unambiguously image the “physical” interface position between Si and furnace grown layers. The effect of postoxidation annealing on the interface roughness of was studied with this technique. While no obvious effect due to postoxidation annealing on roughness was observed for silicon (111) a postoxidation annealing at 900°C dramatically removed roughness at interfaces. A model was developed to explain our experimental results based on the idea of kinetic smoothening and oxidation induced roughening. Qualitative agreement has been reached. © 1999 The Electrochemical Society. All rights reserved.

Effects of Oxidation Ambient and Low Temperature Post Oxidation Anneal on the Silicon/Oxide Interface Structure and the Electrical Properties of the Thin Gate Oxide

Electrical properties of ultra thin gate oxide in thickness of 4 to 10 nm have been evaluated, manufactured either by wet or dry oxidation process. The relationship between silicon/oxide interfacial structure and the electrical properties was analyzed. In addition, the effect of post oxidation annealing (POA) temperature on improvement of the electrical characteristics of the gate oxide has been evaluated when the temperature was lower than 950°C, the conventional POA temperature. The leakage current of the ultra thin gate oxide was found to increase as the thickness decreased. The accelerated degradation of breakdown characteristics was observed as the thickness decreased below 7 nm. The physical properties of the silicon/oxide interface were found to depend on oxidation ambient and POA temperature. The wet oxidation process resulted in a smoother surface than the dry oxidation process did. The POA treatment further decreased the micro-roughness of the silicon/oxide interface. The electrical properties of the gate oxide were found to be closely related to the micro-roughness of the silicon/oxide interface. Good electrical properties were obtained for the gate oxide manufactured by the wet oxidation process followed by the POA treatment at 850°C.

Effect of postoxidation annealing on the reliability of rapid thermal thin gate oxides

The reliability of thin gate oxides grown by rapid thermal oxidation in O/sub 2/ followed by one and two step postoxidation annealing (POA) in N/sub 2/ was studied. The one step POA was carried out by switching O/sub 2/ into N/sub 2/ immediately after oxidation without changing temperature, while the two step POA was cooled down first and subsequently heated to the same temperature as oxidation in N/sub 2/. It was experimentally observed that the oxide thickness increases significantly with the POA time in one step POA, while the oxide thickness shows very little change during two step POA. The interfacial properties and the oxide breakdown endurance can be improved by the two step POA. Also, the radiation hardness of oxide is less degraded by the two step POA than by one step POA. The effect of oxide thickness variation due to POA is chiefly responsible for the observation and is important to thin gate oxides.

Re-evaluation of the benefits of postoxidation annealing on sub-100 /spl Aring/ gate oxide quality

The effects of postoxidation annealing (POA) on thin gate oxide quality are evaluated in two different MOS integration schemes. One scheme involves a high temperature backend step consisting of a 20-s 1065/spl deg/C rapid thermal anneal after gate polysilicon deposition. The second involves a much lower temperature backend step consisting of a 20-s 800-850/spl deg/C rapid thermal anneal. It is demonstrated that although the POA significantly improves dielectric properties such as charge to breakdown and interface hardness at very low backend temperatures, it does little to improve such properties at high backend temperatures. Given that typical semiconductor processes often include thermal steps that exceed gate oxidation temperatures, it may be possible to eliminate POA with no adverse effects. Eliminating POA can in turn reduce processing time and further reduce total thermal budget.

Improvement of Ultrathin Oxides by Post-Oxidation Annealing

AbstractThe low temperature oxidation is effective for the atomically-controlled gate oxide growth. We focused the effects of post-oxidation annealing (POA) and attempted to improve the properties of the low-temperature-grown ultrathin oxides with a thickness of 3nm by POA. POA abruptly reduced the leakage current at a low gate voltage below 1.5V and the interface trap density. The correlation between the interface trap and the leakage current at a low applied voltage region were confirmed. We found that the stressing immunity of the ultrathin oxides grown at a low temperature, 650°C, is drastically improved by POA at 850°C.

The effect of processing conditions on the structure of buried interfaces between silicon and silicon dioxide

AbstractA transmission electron microscope technique is used to image atomic steps at buried interfaces between silicon and silicon dioxide. We have studied the effect of processing conditions on the interfacial structure of Si/SiO2 with this technique. We observed a dramatic effect of post-oxidation annealing on silicon (100). Roughening of Si(111) interfaces due to chemical preparation is also reported.

Growth of thin thermal silicon dioxide films with low defect density

Abstract The use of thin gate oxides in scaled MOS-VLSI devices demands good control over oxide thickness, oxide defects, hot carrier instability and breakdown behaviour. In the quest to grow high quality SiO 2 films with low defect density, an investigation on the effect of growth and annealing ambients on oxide properties is reported. Thin SiO 2 films (10–60 nm) grown at 900–1000°C in O 2 /O 2 + N 2 were characterized by C-V and I-V techniques using Al/SiO 2 /p-Si and poly-Si/SiO 2 /p-Si structures. Quality oxides with a very low density of physical defects due to contamination/pinholes (responsible for dielectric breakdown at fields lower than the intrinsic breakdown fields), H 2 O-related and intrinsic defects (acting as electron and hole traps) have been demonstrated. The effect of post-oxidation annealing in N 2 and O 2 on defect-related low-field and intrinsic breakdown behaviour was studied. The occurrence of low-field pre-breakdowns can be reduced by a short O 2 anneal, in agreement with our earlier results. Oxide device worthiness was tested by fabricating N-MOSFETs.

Radiation Response of Thin Oxides Grown By Rapid Thermal Oxidation and Rapid Thermal Annealing Techniques

AbstractHigh quality, 20 to 30 nm thick SiO2 films were grown using rapid thermal oxidation techniques. Metal-oxide-semiconductor (MOS) capacitors formed with these oxides were characterized electrically using low and high frequency capacitance measurements. The effects of post oxidation annealing (POA) ambient, temperature and duration on the initial oxide properties and the radiation response of the MOS capacitors were determined. The addition of a small amount of O2 to the POA ambient significantly reduced the radiation induced hole trapping and interface state creation, particularly for the higher POA temperatures. In addition, annealing and reirradiation experiments were carried out and showed that both the trapped charge and interface state buildup were completely reversible after anneals at 400°C. This repeatability argues against interface state creation models which involve irreversible changes in the atomic arrangements near the interface.

Intrinsic SiO2 film stress measurements on thermally oxidized Si

We have investigated the effects of varying Si oxidation conditions on intrinsic film stress for SiO2 films formed on Si. This study includes stress measurements on four Si orientations: (100), (110), (111), and (311); at oxidation temperatures ranging from 700 to 1100 °C; wet (H2O) versus dry (O2) oxidations for (100) and (111) surfaces; and the effects of postoxidation annealing on stress. We find the following orientation dependence for intrinsic stress measured as a function of oxidation temperature: (110)≥(311)≥(100)&amp;gt;(111); a reduction in stress for wet versus dry studies; and an even larger reduction for postoxidation anneals. A recently proposed step model accounts for the differences in stress between the (111) and the remaining Si orientations. A number of Si oxidation models based on intrinsic stress are compared in their ability to describe observed kinetic behavior, and we conclude that within the Deal–Grove oxidation model, the linear rate constant is strongly influenced by stress in the initial regime while stress is also likely to be important for thicker films.