Effective Gate Research Articles

The Effectiveness of Game Based Learning on The Logic Gate Topics

This article focuses on analyzing the effectiveness of applying Game Based Learning on Logic Gate Material to student learning outcomes. This type of research is quantitative descriptive. This study uses a one group pretest and posttest design. This study uses a one group pretest and posttest design. The treatment given in this research is the application of game based learning. Game based learning using the game “Circuit Scramble.apk. This research was conducted at the Physics Education Study Program at Lambung Mangkurat University. The research subjects are Physics education students taking digital electronics courses in 2019. Data is collected using pre-test and post-test about logic gate. Pre-test and post-test data were tested for normality then N-gain test. N-gain test results obtained a value of 0.703. Therefore, it can be concluded that the effectiveness of the application of game based learning is in the high category. Thus, Game based learning on effective logic gate material is applied to improve student learning outcomes.

A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si With High Etching Selectivity and Isotropy

A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped ${n}^{+}$ poly-Si deposition followed by a subsequentshallow implantation of BF $_{{2}}^{+}$ . Both high etching isotropy in ${n}^{+}$ poly-Si and high etching selectivity between ${n}^{+}$ poly-Si and B-doped poly-Si in a Cl2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of $0.15~\mu \text{m}$ . The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications.

Augmentation and Assessment of a Universal FET ${I}$ –${V}$ Model for Simulating GaN HEMTs

The ON-state ${I}$ – ${V}$ characteristics of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are affected by the bias dependencies of four parameters, namely—virtual gate length, mobility, saturation velocity, and the channel-length modulation (CLM) parameter—this is in addition to the source/drain resistance, CLM, and self-heating which affect all FETs. The existing modeling approach involves developing an equation that includes all the above effects and then extracting all the equation parameters from measured ${I}$ – ${V}$ data. In this approach, at times, some effects need to be neglected in the quest for simplicity, and the values of some extracted parameters influence each other. To mitigate this problem, we propose a flipped modeling approach. Here, first, discrete data regarding the above four bias dependencies is extracted from the measured ${I}$ – ${V}$ curves using a universal FET model (UFM) which captures effects common to all the FETs. Next, the extracted data of each bias dependence is fitted using a simple equation with qualitatively correct behavior; these curve-fit equations are augmented to the UFM to complete the model. The CLM and saturation velocity data are extracted from the remnants of calibrated 2-D numerical simulations after turning off the virtual gate and self-heating effects. The parameter values of different devices and models are compared.

Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances

To remove simultaneously the ambipolar conduction and enhance HF performances, we propose a promising configuration of DG-TFET with asymmetric gate–drain overlap (ASGDO DG-TFET) in which only back gate is overlapped with drain region. This proposed structure of DG-TFET removes the trade-off between ambipolarity and HF performances by taking the merit of gate–drain overlap in terms of reduction in ambipolarity and suppressing its demerit with reduced gate–drain parasitic capacitance. Using 2-D simulation, it is observed that ambipolar conduction can be suppressed to a large extent in DG-TFET with only 20 nm of back gate–drain overlap, thus not limiting the scaling of drain region compared to symmetric gate–drain overlap DG-TFET (SGDO DG-TFET). Due to the presence of enhanced depletion layer in the drain region caused by a large vertical electrical field, tunneling width at drain–channel interface is found to be maximum in the proposed device, which eventually prevents the charge carriers to tunnel. Furthermore, ASGDO improves the HF performance parameters such as cutoff frequency and gain–bandwidth product compared to SGDO due to reduction in gate–drain parasitic capacitance, and this improvement is found to be consistent while scaling down the channel length.

Ultrasensitive Multilayer MoS2‐Based Photodetector with Permanently Grounded Gate Effect

Abstract2D materials, specifically MoS2 semiconductors, have received tremendous attention for photo‐sensing applications due to their tunable bandgap and low noise levels. A unique photodetector using multilayer MoS2 as the semiconductor channel, in which the gate electrode of the device is permanently connected to the grounded source electrode to introduce rectification, is reported. The proposed grounded‐gate photodiode exhibits high photoresponsivity of 1.031 A W−1, excellent photodetectivity (>6 × 1010 jones), and highly stable rise/fall time response (100–200 ms) under illumination of visible light (at the wavelengths of 405, 532, and 638 nm). Numerical device simulations using quantum transport methods and photoconductive effects are used to explain the device operation. It is also suggested that the gate metal work function can be carefully chosen to increase the sensitivity of the grounded‐gate photodetector by suppressing the dark current. The grounded‐gate device proposed, owing to the properties of rectifying behavior, low contact resistance, consistent photoresponsivity, and linear sensitivity, provides a new platform for next‐generation applications in the field of electronics and optoelectronics.

Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET

A small signal equivalent model of surrounding gate MOSFET incorporating fringing capacitances has been proposed and detailed in this paper. Detail modeling of the fringing (outer and inner both) capacitances of surrounding gate MOSFETs are considered here. Considering fringing capacitance, also the gate to drain/source and effective gate capacitances have been calculated for the proposed model. Low frequency Y-parameters (admittance parameters) of the SRG MOSFET are derived from the proposed model and expressed using real/imaginary function for different biasing condition. RF/analog performance parameters like Gate input capacitance (CGG), transport time delay (τ), input resistance (Rin), trans-conductance (gm), channel conductance (gds) etc have been evaluated. Figure of Merit (FOM) parameters like cut off frequency, gmRo, maximum oscillation frequency etc of the proposed model has been evaluated to study the effect of parasitic capacitances on the RF performances in depth. Extensive simulations using Silvaco ATLAS have been done to verify the proposed models. Matching of the simulated results with the model data demonstrate the correctness of the proposed model. It has been observed that the fringing capacitances can deteriorate the ac characteristics of the nano dimensional surrounding/cylindrical gate MOSFET.

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via device simulation, was considered, and it demonstrates that the double-gate hetero-junction tunnel FET has a substantial capacitance merit compared to CMOS transistors. The early stages of our work used the intrinsic delay for device optimization, as defined in the international technology roadmap for semiconductors. However, based on the comparison with the speed evaluation results of the ring oscillator, the device optimization scheme was improved. This was achieved by adopting a new effective delay index, based on the effective on-currents and effective gate capacitances. Studies on the CMOS device design also applied the concept of effective on-current; however, the design method presented herein is novel in that it introduced the concept of effective gate capacitance.

Three-Terminal Si/SiC Hybrid Switch

A Si/SiC hybrid switch is an innovative power semiconductor switch realized by paralleling a Si insulated-gate bipolar transistor (IGBT) and a SiC device (metal-oxide semiconductor field-effect transistor ( mosfet ) or junction field-effect transistor). The Si/SiC hybrid switch combines advantages of Si IGBT's high conduction capability and SiC device's fast switching speed, and effectively addresses Si IGBT's high turn- off loss issue and SiC mosfet 's high cost concern. However, to control the hybrid switch, two separate gate drivers are usually needed, which increases the complexity and cost. In this letter, a simple and effective gate driver circuit is designed for the Si/SiC hybrid switch, which requires only one control signal and gate driver circuit to drive both Si IGBT and the SiC device, making the hybrid switch a typically three-terminal device. The operation principles and design guidelines are presented and analyzed. A three-terminal 1200-V, 200-A hybrid switch prototype in a half-bridge configuration is developed and experimental results verify its effectiveness.

Error-mitigated quantum gates exceeding physical fidelities in a trapped-ion system

Various quantum applications can be reduced to estimating expectation values, which are inevitably deviated by operational and environmental errors. Although errors can be tackled by quantum error correction, the overheads are far from being affordable for near-term technologies. To alleviate the detrimental effects of errors on the estimation of expectation values, quantum error mitigation techniques have been proposed, which require no additional qubit resources. Here we benchmark the performance of a quantum error mitigation technique based on probabilistic error cancellation in a trapped-ion system. Our results clearly show that effective gate fidelities exceed physical fidelities, i.e., we surpass the break-even point of eliminating gate errors, by programming quantum circuits. The error rates are effectively reduced from (1.10 ± 0.12) × 10−3 to (1.44 ± 5.28) × 10−5 and from (0.99 ± 0.06) × 10−2 to (0.96 ± 0.10) × 10−3 for single- and two-qubit gates, respectively. Our demonstration opens up the possibility of implementing high-fidelity computations on a near-term noisy quantum device.

Giant Conductance Enhancement of Intramolecular Circuits through Interchannel Gating

Summary For neutral intramolecular circuits with two constitutionally identical branches, a maximum 4-fold increase in total conductance can be obtained according to constructive quantum interference (CQI). For charged intramolecular circuits, however, the strong electrostatic interactions entangle the quantum states of these two parallel pathways, thus introducing complicated transport behavior that warrants experimental investigation of the intramolecular circuit rules. Here, we report that a tetracationic cyclophane with parallel channels exhibits a 50-fold conductance enhancement compared with that of a single-channel control, an observation that supplements intramolecular circuit law in systems with strong Coulombic interactions. Flicker noise measurements and theoretical calculations show that strong electrostatic interactions between charged parallel channels—serving as the chemical gate to promote the effective conductance of each channel—and CQI boosts the total conductance of the two-channel circuit. The molecular design presented herein constitutes a proof-of-principle approach to charged intramolecular circuits that are desirable for quantum circuits and devices.

Mechanisms of a Rectifying TiN Gate Contact for AlGaN$/$GaN HEMTs on Silicon Substrate

Rectifying Titanium Nitride (TiN) gate contact technology is developed for AlGaN $/$ GaN based micro and nanometer HEMTs. A high compressive strain occurring in thinner TiN films (ranging from 5 nm to 60 nm), deposited by sputtering, leads to a reduction in tensile strain at the surface of AlGaN barrier. The diminution in tensile strain forms a pseudo- $p$ -type layer (diode-like). This strain reduction has no effect on the bandgap of the AlGaN barrier layer, allowing the gate to withstand a reverse gate bias larger than 100 V. Characterization using the high-resolution transmission electron microscopy combined with the X-ray photoelectron spectroscopy reveals a good TiN $/$ AlGaN interface quality and no diffusion of TiN into AlGaN. The effective energy barrier of the rectifying nanoscale TiN gate contact has a relatively large height of 1.1 eV associated with an ideality factor of 1.4. A dramatic drop of the reverse-bias leakage current down to 11 pA $/$ mm is measured at −30 V. In addition, electrical measurements show very low gate and drain lag effects of 4.2 ${\%}$ and 6.7 ${\%}$ , respectively.

IoT feasibility aspects of mold temperature monitoring and casting simulation for smart foundry

The world is moving in the direction of digitalization demanding change to smart manufacturing. Utilization of smart manufacturing with adoption of Internet of Things (IoT) in the foundry industry gives benefits and help to overcome challenges. In cast iron foundry rejection due to solidification defect like sand drop, crack, pinholes, shrinkage cavity, cold shut, misrun which can be reduced with help of directional solidification. For solidification analysis cooling curve monitoring needs time and effort. For analysis the correct method of data collection and monitor is required. In present work authors have made an attempt to use solution that is anticipated is Autocast_X1 software simulation and development of low cost IoT solution for smart foundry. In Autocast-X1 software simulation is performed and defect analysis is carried out. It is the effective way to improve design and helps to reduce trial runs and efforts. Thermocouple directly placed in a mould cavity to monitor temperature. It is helpful to study cooling curves and quality check of solidification defects. Experimental investigations are carried out to map simulation result of mold temperature with real time data with help of thermocouples placed at mold interface. Mold-metal interface data using controllers and amplifier are stored in mobile for live monitoring. Use low cost IoT platform reduces supervisor movement and saves time by providing casting solidification data at his work place. With the help of casting simulation early check of effective gating system and defect prediction enables reasonable productivity and quality. IoT solution helps to monitor foundry practices, reduction in human effort, paperwork, and reduction in cost with rise of profit margin.

Dimension Scaling Effects on Conduction and Low Frequency Noise Characteristics of ITO-Stabilized ZnO Thin Film Transistors

Conduction characteristics and low frequency noises in ITO-stabilized ZnO thin film transistors (TFTs) with constant channel width (W=50 μm) and different channel lengths (L=5, 10, 25, 50 and 100 μm) are measured and analysis. Firstly, dependences of threshold voltage and field effect mobility on channel length are examined. With decreasing channel length, the threshold voltage shifts to the negative direction which may attribute to carrier diffusion from source/drain to the intrinsic device channel. In addition, significant degradation of field effect mobility is observed in short channel device which are induced by the presence of series contact resistance. The value of contact resistance has also been extracted. Secondly, the drain current noise power spectral densities (S ID ) are measured at varied effective gate voltages. The measured noises follow a 1/f γ and y is about -1.1. Moreover, the normalized noises (S ID /I ds ) are dependent linearly on the inverse of channel length and the slope is about -0.75. Finally, the dominant mechanism of low frequency noise in ITO-stabilized ZnO thin film transistor are examined. The slope of normalized noise against effective gate voltage are extracted, which are varied from -1.03 to -1.84 with decreasing channel length and thus it indicates that ITO-stabilized ZnO TFTs varied from bulk dominated devices to interface dominated devices. By using of ΔN-Δμ model, the normalized noises are simulated by considering of contact resistance. Several noise parameters (flat-band voltage noise spectral density, etc) are extracted and analysis.

Design of XOR and XNOR Based Full Adder Circuits

This paper has a XOR / XNOR gate circuits produces separate and establishes a simultaneous XOR - XNOR function.. Due to stubby yield capacity and short-circuit energy dissipation, the power utilization and latency of these circuits is increasing A new one-bit adder hybrid circuit is chosen built on the effective gates of xor xnor or xor / xnor. Each prefer circuit has its own advantages as it is known for its high speed, low current drain, short delay product (PDP), galvanic ability, etc. Simulations of the planned models were carried out using Mentor Graphics to see the quality of these projects. The simulation results are based on the 130-nm CMOS engineering design. A recent technique of transistor sizing is implemented to improve the circuits ' PDP.

Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETs

Source/drain (S/D) variations in sub-5-nm node fin and nanosheet field-effect transistors (NSFETs) were thoroughly analyzed by using fully calibrated technology computer-aided design (TCAD). S/D open and contact critical dimensions (OCD and CCD) vary during anisotropic etching for silicide and S/D epi formations, respectively, and these vary dc/ac performances. OCD varies S/D resistances and parasitic capacitances, but slight RC delay variations occur. CCD affects OFF-state currents ( ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ ) and RC delay, but differently in terms of fin field-effect transistors (FinFETs) and NSFETs. As the S/D epi enlarges by CCD changes, high subfin leakage of FinFETs flows into the fin bottom regions, thus varying ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ greatly. NSFETs have the dielectric layers beneath the S/D epi; therefore, the ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ variations are smaller. Both effective currents ( ${I}_{{\text {eff}}}$ ) and gate capacitances ( ${C}_{{\text {gg}}}$ ) of FinFETs vary in the same direction, whereas the NSFETs have constant ${C}_{{\text {gg}}}$ with respect to CCD changes because of the tradeoff between the intrinsic and parasitic capacitances. Although this effect increases the RC delay variations of the NSFETs, p-type FinFETs have the largest RC delay variations due to the greatest relative variations of ${I}_{{\text {eff}}}$ . Thus, the NSFETs are much immune to CCD variations compared with FinFETs in terms of ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ and RC delay.

Superconducting size effect in thin films under electric field: Mean-field self-consistent model

We consider effects of an externally applied electrostatic field on superconductivity, self-consistently within a BCS mean field model, for a clean 3D metal thin film. The electrostatic change in superconducting condensation energy scales as $\mu^{-1}$ close to subband edges as a function of the Fermi energy $\mu$, and follows 3D scaling $\mu^{-2}$ away from them. We discuss nonlinearities beyond gate effect, and contrast results to recent experiments.

Superior Transient Response to Heavy-Ion Irradiation by N-Channel SOI-iFinFETs

In this paper, we for the first time report the transient response of SOI-iFinFETs under heavy-ion radiation conditions. Using calibrated 3-D TCAD simulations, we analyze the radiation performance of advanced multi-gate devices such as SOI-FinFET and iFinFETs, which conform to 14 nm technology node. The transient response of FinFETs, and iFinFETs with varying number of inserted oxide regions, is reported under heavy-ion irradiation. The effective fin width and gate length scaling has also been reported for FinFET and iFinFETs under heavy-ion irradiation. Our results show that iFinFETs are better suited for heavy-ion radiation environments as compared to FinFETs due to the presence of inserted oxide in between the fin regions. The iFinFETs show up to 28% less peak drain current generated due to heavy-ion with LET = 10 MeV-cm2/mg as compared to FinFETs. We also show that iFinFET architecture brings more advantage to radiation performance over conventional FinFETs for narrow fin devices, while gate length scaling has similar radiation response for both FinFET and iFinFETs.

A Gate Drive Circuit and Dynamic Voltage Balancing Control Method Suitable for Series-Connected SiC mosfets

Compared with silicon insulated-gate bipolar transistor, silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor ( mosfet ) presents good features that it clearly shows on its switching and thermal performance. However, the fast switching speed of SiC mosfet makes it much more difficult for solving the dynamic voltage imbalance problem caused by the parameter fluctuations of the SiC mosfet s and drive circuits when they are connected in series. This article proposes an effective gate drive circuit and its dynamic voltage balancing control method to tackle this issue. The proposed method not only balances the dynamic voltage during high-speed switching but also adapts to the variation of the dc-bus voltage by utilization of overdrive control method (ODCM). Furthermore, to widen the control range of the ODCM, a switched-capacitor compensation method by switching and combining different drive capacitors into different values is proposed. The operation principles and the parameter design method are discussed in detail. The performance of the proposed series-connected SiC mosfet s gate drive circuit and its dynamic voltage balancing control method is validated by experimental results. The dynamic voltage can be well balanced within the design range.

Simulation and Performance Evaluation of In Ga P/In Ga As/Ga As Dual Channel HEMT

An InGaP/InGaAs/GaAs dual channel High Electron Mobility transistor (HEMT) with three δ doped layers with different doping densities is modeled and simulated in this paper by using two dimensional ATLAS simulation package from Silvaco software. Different DC performances (Drain characteristic and Transfer characteristics) at various voltage levels are analyzed and results are compared by taking the gate length of 500nm and 800nm at two different temperature levels (250k and 300k) to determine the efficiency of the device for high speed digital device applications. The paper describes the effect of parasitic access resistance on device gate length and effect of mobility by varying temperature. High drain current drivability, large carrier densities and better saturation characteristics are realized because of the inclusion of InGaAs channel instead of GaAs DC structure and schottky behavior of InGaP layer. The studied double channel HEMT with proper dimensions and accurate doping profile makes it a promising device for high performance electronics device applications.

Study of work-function variation in stacked multiple-channel-structure device

For stacked multiple-channel-structure devices such as stacked nanowire FETs (stacked NWFETs), work-function variation induced (WFV-induced) threshold voltage (VT) variation is quantitatively investigated using a three-dimensional technology computer aided design (TCAD) tool. In the stacked structure device, the more nanowires are stacked, the more the WFV-induced VT variation can be decreased. It is proposed that the ratio of average grain size to gate area (RGG) for stacked multiple channel structures can be used to estimate the WFV-induced VT variation. For accurate estimation, the effective gate area (GAeff) should be considered in the stacked structure, as the variation is averaged out by stacking multiple channels. If two 3-stacked NWFETs have the same GAeff but different nanowire diameters (i.e. one with 10/10/10 nm and the other with 7/9.34/13 nm), the two would have identical WFV-induced VT variation. In this context, if a single NWFET and a 2-stacked NWFET have identical GAeff, the two would have the same VT variation. Using the RGG concept with GAeff enables the WFV-induced VT variation to be precisely estimated, regardless of nanowire diameter and the number of nanowires.