Edge Termination Structure Research Articles

(Invited) Three-Section Adjusted Field Limited Rings Applicable for SiC 2200V Power MOSFETs

A novel edge termination structure with three-section adjusted field limited rings (TS-FLRs) is proposed and fabricated for 2200V SiC power MOSFET. The TS-FLRs feature three sections with different width and space of FLR, which significantly reduces design difficulty of FLR technique and effectively modulates electric field distribution inside termination region. Moreover, the TS-FLRs are investigated comprehensively by simulation, showing a good tradeoff between the process tolerance, the design difficulty, and the performance as comparison with fixed space FLRs (F-FLRs). Experimental results show the TS-FLR structure enclosing the SiC power MOSFET achieves the breakdown voltage of 2500V, 20% and 45% higher than F-FLRs (space=2μm and 1.3μm, respectively).

Examining Edge-Termination Performance and Failure in Vertical GaN and AlGaN Power Diodes Using Scanning-Beam Techniques

Abstract This article discusses the use of scanning-beam techniques such as EBIC, IBIC, and OBIC to optimize the design of edge-termination structures in vertical GaN and AlGaN power diodes.

A robust and area-efficient guard ring edge termination technique for 4H-SiC power MOSFETs

A robust and area efficient adjusted multi-section guard rings (AMS) edge termination structure is employed to a 4H-SiC power MOSFET device rated at 1.7kV and fabricated without extra process steps or masks in this paper. The lightly doped p-type guard ring with adjusted multi-section spacing, which is similar with varied lateral doping technology widely used in silicon edge termination, creates a smoother and more uniform surface electric field distribution across all rings, resulting in a higher reverse blocking voltage with minimal edge termination area. The fabricated AMS-MOSFET devices with an active area of 2.5mm2 have reverse blocking voltage up to 2.5kV at room temperature. Compared to the conventional SiC MOSFETs with the uniform ring spacing, the AMS-MOSFET with the same edge termination area shows more than a 25% increase in the reverse blocking voltage. Furthermore, high-temperature reverse bias stress test is performed to verify junction and termination robustness of the AMS-MOSFET device. A small variation in the reverse blocking voltage and drain-source leakage current are achieved under 168h high-temperature reverse bias stress with the drain bias of 1360V at ambient temperature of 175°C, which suggests an expected robustness in high power application for the fabricated SiC MOSFET with the AMS structure.

3-D Edge Termination Design and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ -BV Model of A 700-V Triple RESURF LDMOS With N-Type Top Layer

3-D edge termination design and analytic model for specific on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}})$ versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters ${L}_{1}$ and ${L}_{2}$ in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at ${L}_{1} = 30~\mu \text{m}$ and ${L}_{2} = 1~\mu \text{m}$ . On the other hand, an analytic model is developed to describe the relation between ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV, which is obtained as ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2}$ and theoretically verifies that the fabricated device has achieved optimized ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 86.49 $\text{m}\Omega ~\cdot $ cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data.

High Voltage Diodes in Diamond Using (100)- and (111)- Substrates

We present a comparative study of PIN structures in diamond on type IIa (100)- and type IIb (111)- oriented bulk diamond substrates. An 8.5- $\mu \text{m}$ thick i-layer demonstrated a blocking voltage>1kV for the (100)-oriented diamond sample without any mesa isolation, passivation, or edge termination structures. PIN diodes with a 530nm thick drift region, on the (111)- sample, demonstrated a blocking voltage of 207V at a current level of 1A/cm2 with a corresponding blocking electric field of 3.9MV/cm. A deep ultraviolet light emission was observed only in (111)-diodes under forward bias, confirming well-behaved p-n junction characteristics in (111) as compared to (100).

A Comparative Study 4500-V Edge Termination Techniques for SiC Devices

This paper compares five edge termination techniques for SiC high-voltage devices: single zone junction termination extension (JTE), ring assisted-JTE (RA-JTE), multiple floating zone-JTE, hybrid-JTE, and floating field rings. PiN diodes with these edge terminations were fabricated on a 4.5kV-rated 4H-silicon carbide (4H-SiC) epi-layer. It was experimentally demonstrated that the Hybrid-JTE provides a nearly ideal breakdown voltage (~ 99% of the ideal parallel plane breakdown voltage) with a stable avalanche blocking behavior. RA-JTE, with tight control of the JTE implant dose, is demonstrated to be the most area-efficient edge termination structure for SiC power devices.

Design and Characterization of Sloped-Field-Plate Enhanced Trench Edge Termination

In this paper, the design and characterization of the sloped-field-plate enhanced trench edge termination structure are carried out. For achieving the ideal planar junction breakdown voltage and high dV / dt performance, structural parameters, including the depth of the sloped-field-plate and the depth and width of the trench, need to be well designed. Using extensive numerical simulations, the above-mentioned design is accomplished. Experimental results show that for 600 V class devices, a breakdown voltage of 757 V can be achieved by the devices with a trench width larger than 20 $\mu \text{m}$ . The breakdown characteristics are verified as the ideal planar junction breakdown by using liquid crystal thermal measurement. Furthermore, the high dV / dt measurement results show that the devices with a trench width larger than 25 $\mu \text{m}$ are capable of handling a high dV / dt of 28.9 kV/ $\mu \text{s}$ even at a bus voltage of 750 V.

Ultrahigh-Voltage SiC MPS Diodes With Hybrid Unipolar/Bipolar Operation

In this paper, ultrahigh-voltage (UHV) SiC devices with hybrid unipolar/bipolar operation are introduced and demonstrated. As the first step of such a device, a merged p-i-n Schottky (MPS) diode with an epitaxial p+-anode layer is proposed to reduce the conduction loss of a bipolar device in the low current region. A “snapback” phenomenon is intensively investigated by analytical modeling, device simulation, and experiment and a design guideline of snapback-free hybrid operating MPS diodes is presented. Using the design guideline, snapback-free MPS diodes are fabricated and forward characteristics are investigated. By using a proper edge termination structure, a UHV SiC MPS diode with breakdown voltage of 11.3 kV is demonstrated.

A Study of Oxide Etch Angle of Edge Termination Field Plate for Fabrication of SiC SBD

The silicon carbide (SiC) material is being spotlighted as a next-generation power semiconductor material due to the characteristic limitations of the existing silicon materials. SiC has a wider band gap, higher breakdown voltage, higher thermal conductivity, and higher saturation electron mobility than Si. However, actual SiC SBDs exhibit a lower dielectric breakdown voltage than the theoretical breakdown voltage that causes the electric field concentration, a phenomenon that occurs on the edge of the contact surface as in the conventional power semiconductor devices. In this paper, we designed an edge termination structure using a field plate structure through oxide etch angle control, and optimized the structure to obtain a high breakdown voltage. The experiment results indicated that oxide etch angle was 45° when the breakdown voltage characteristics of the SiC SBD were optimized and a breakdown voltage of 681V was obtained.

Planar edge terminations for high voltage 4H-SiC power MOSFETs

Several edge termination structures for high voltage 4H-SiC devices compatible with a planar power MOSFET fabrication process are analyzed in this paper. The edge terminations’ efficiency has been experimentally demonstrated on PiN diodes with breakdown voltage capabilities ranging from 2 to 5 kV, fabricated within a full power MOSFET process technology. The studied edge terminations consist of typical JTEs, novel FGRs using MOSFET P-well implantation, as well as a combination of JTEs and FGRs. The experimental results have shown a good efficiency of most of the implemented edge terminations. It is also shown that P-well FGRs could be an effective cost solution for high voltage SiC based power MOSFETs. Moreover, the edge termination combining JTEs and FGRs concepts shows a better tolerance of breakdown voltage values against variations in the JTE dose. The same edge termination design allows one to obtain a good efficiency for both 1.7 and 4.5 kV PiN diodes. The optimal termination has been successfully implemented on 4.5 kV power MOSFETs.

Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme

This letter reports a new 900 V 4H-SiC JBSFET containing an MOSFET with an integrated JBS diode in the center area of the chip. Both MOSFET and JBS diode structures utilize the same edge termination structure,which results in 30% reduction in SiC wafer area consumption in case of 10 A rating device. In order to form a Schottky contact for the JBS diode as well as ohmic contacts for n+ source and p+ body of the MOSFET,a simple metal process flow has been newly developed. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). The proposed JBSFET was successfully fabricated using a nine-mask on 6-in 4H-SiC wafers.

A Novel Sloped Field Plate-Enhanced Ultra-Short Edge Termination Structure

A novel sloped field plate (FP)-enhanced ultra-short edge termination structure is proposed and experimentally demonstrated. The structure features a benzocyclobutene dielectric filled trench, and is fabricated along with a high-voltage p-i-n diode. In addition, a sloped FP is put inside the trench and connected to the anode electrode. The fabricated device shows a breakdown voltage of 755 V, and is confirmed as the ideal planar junction breakdown voltage of the p-i-n diode. The proposed edge termination structure has a total width of $35~\mu \text{m}$ , which is $\sim 1$ /5 the size of a conventional termination structure using the guard rings approach.

Static and Dynamic Characteristics of SiC MOSFETs and SBDs for 3.3 kV 400 A Full SiC Modules

Characteristics of SiC MOSFETs and SBDs with 3.3 kV-class have been presented. Static Characteristics of the MOSFET showed a specific on-resistance of 14.2 mΩ cm2. A breakdown voltage of 3850 V is obtained by using the dose optimized edge termination structure as we have previously reported [1]. At the same time, reverse leakage current of the 3.3 kV SiC SBDs can be suppressed by the JBS structure and the edge termination which is also used in the MOSFETs. By using the MOSFETs and SBDs, we have demonstrated the superior capability of the 3.3 kV 400 A full SiC 2 in 1 modules with a compatible case and terminal configurations to Si IGBT modules. Dynamic characteristics of the full SiC module in an inductive load switching exhibits superior turn-on and turn-off properties even at a high drain voltage of 1650 V, demonstrating the availability of high voltage SiC power systems.

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.

Metropolis Monte Carlo Search for Non-Precious Metal Catalyst Active Site Candidates

Non-precious metal oxygen-reduction catalysts have the potential to out-perform the rare and expensive platinum group metals used for oxygen reduction reaction at the cathode of low temperature polymer electrolyte fuel cells. Understanding and optimizing non-precious metal catalyst activity is dependent upon an atomistic understanding of active site structures. Unfortunately, there exists a tremendously large configurational active site search space comprised of C, N, Fe (and/or Co), and a variety of edge termination and defect structures. We here present a stochastic search methodology that we have developed and applied to identification of candidate structure attributes using graphene as a template matrix material.

Design, Fabrication, and Characterization of Ni/4H-SiC (0001) Schottky Diodes Array Equipped With Field Plate and Floating Guard Ring Edge Termination Structures

In this paper, a through process for a commercial fabrication of a Schottky diodes array on thick epitaxial (50 $\mu{\rm m}$ ) 4H-SiC (0001) is presented. Nickel was used as a Schottky contact, while a tri-layer of Ti/Pt/Au was considered for ohmic contact metallization. An oxide field plate edge termination and floating metal guard ring was integrated simultaneously in each device structure. Moreover, to improve the device reliability, an optimum thickness of field plate (composite layer of thermally grown oxide and plasma enhanced chemical vapor deposition oxide) was introduced. The process-induced carbon-oxides contamination was eradicated by vacuum annealing at a mild temperature. The critical values of device parameters, such as leakage current, breakdown voltage $(V_{BV})$ , Schottky barrier height $(\phi_{B})$ , ideality factor $(\eta)$ , and epitaxial doping concentration $(N_{D})$ , were obtained from experimentally measured current–voltage $(I{\hbox{--}}V)$ and capacitance–voltage $(C{\hbox{--}}V)$ characteristics. The data revealed that $\phi_{B}$ , $\eta$ , $V_{BV}$ , and reverse leakage current are 1.34 eV, 1.21, ${>}{\rm 800}~{\rm V}$ , and 900 pA (at ${-}{\rm 100}~{\rm V}$ ), respectively, which suits most commercial aspects.

Copper Oxide Edge-Termination for GaN Schottky Barrier Diodes with Low Turn-on Voltage

ABSTRACTIn this study, we propose copper oxide (CuOx) edge-termination for GaN-based Schottky barrier diodes (SBDs) with low turn-on voltage. CuOx fabricated by thermal oxidization of sputtered Cu film at 275°C consisted mainly of Cu2O which is known as a p-type semiconductor. We applied CuOx edge-termination to GaN SBDs with tantalum (Ta) Schottky electrode which has low work function of 4.25 eV. The experimental results of current-voltage characteristics insisted that CuOx edge-termination structure was effective to increase breakdown voltage of GaN SBDs with keeping low turn-on voltage of 0.29 V at 10 A/cm2.

Electric field unbalance for robust floating ring termination

The electric field balancing in the guard-ring edge termination structure of 600V class Super-Junction devices is studied. The relation of the lateral electric field across the racetrack structure and the robustness of the structure against avalanche currents is investigated through experimental data and TCAD simulations. It has been found that the electrical field must be substantially imbalanced to achieve good ruggedness. The effect of the P-ring dose on the electrical performances of punch-through PiN diodes is also investigated.

Investigation of the Suitability of 1200-V Normally-Off Recessed-Implanted-Gate SiC VJFETs for Efficient Power-Switching Applications

A recessed-implanted-gate (RIG) 1290-V normally-off (N-OFF) 4H-SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFET's on-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high on-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific ON-state resistance from 2.2 to 1.5 mOmega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.

Breakdown Voltage Characteristics of FLR-Assisted SiC-SBD Formed by Aluminum Metal Junction Edge Termination

This paper demonstrates the breakdown voltage characteristics of different edge termination structures including aluminum (Al)-deposited guard ring and Al-deposited guard ringassisted field limiting ring (FLR) for a 4H silicon carbide (SiC) Schottky barrier diode (SBD). In order to investigate the application feasibility of the Al-deposited junction termination to a high breakdown voltage SiC-SBD, two types of SiC-SBDs are fabricated using conventional photolithography, electron beam evaporation, and thermal treatment techniques without ion implantation and thermal oxidation procedures. The breakdown voltage characteristics of the SiCSBDs are significantly dependent on the Al-deposited edge termination. The SiC-SBD without the Al-deposited edge termination shows less than 250 V breakdown voltage, while the Al-deposited guard ring and Al-deposited guard ring-assisted FLR structures show roughly 700 V and 1200 V breakdown voltages, respectively. The prominent improvement in the breakdown voltage characteristics is attributed to the electric field lowering at the Schottky contact edge by the Al deposition edge termination.