East Fishkill Research Articles

The First Thin Film Electronic Package

The magnetic thin-film head, announced by IBM in 1979, marked the transformation of electrochemical technology from a shop art to a precision manufacturing process with far wider applications than the thin film head. An important application of electroplating was in the fabrication of the multichip module that provided the packaging for chips in advanced computers. These modules included copper strip lines for data transmission between chips. To minimize pulse distortion, these lines had to have precisely controlled propagation characteristics, and plating through a lithographic mask was the most effective way to insure the tight control on the geometry of the lines necessary to meet this requirement. This paper highlights the evolution of packaging for computers and tells how the scientists and engineers from the IBM T.J. Watson Research Center who had created the thin film head, worked with the development and manufacturing groups at IBM’s East Fishkill plant to bring electrochemistry into the manufacture of advanced packaging modules.

The First Thin Film Electronic Package: From Invention to Manufacturing

As late as the end of the 1970’s, electroplating was regarded as a mystical shop art that had no place in microelectronic fabrication. In 1979 IBM introduced a magnetic thin film head made possible by a newly invented process that was based on electroplating – an achievement that cast electroplating in a new light. Today, electroplating has spread into applications ranging from nanoscale patterning of copper BEOL wiring below 10 nanometers on silicon chips to the deposition of materials for synthesis into photovoltaic layers on 60 cm by 120 cm solar panels, and has also made possible the use of metal structures in MEMS devices. The successful production of the thin film head with its precisely patterned high aspect ratio copper coils and its permalloy elements with tightly controlled magnetic properties, which plating experts of the 1970’s deemed impossible to do by plating, made device fabricators receptive to the electrochemical technology they once shunned.An important new application of electroplating technology was in the fabrication of the multichip module. In advanced computers, these modules were multilayer ceramic structures that provided the power connections to the circuit chips and had a top layer of copper strip lines for data transmission between chips. The strip lines consisted of copper conductors with a rectangular cross-section that might be 6 µm high and 10 to 20 µm wide embedded in polyimide between two ground planes. These structures, which were essentially low-loss transmission lines, had to have precisely controlled propagation characteristics to minimize pulse distortion. Plating through a lithographic mask was an effective way of insuring the tight control on the geometry of the lines necessary to meet this requirement. One aspect of this talk will be to highlight the technical aspects of integrating electrochemical technology into the fabrication process for the transmission lines. The other will address how the scientists and engineers from the IBM T.J. Watson Research Center who had created the thin film head, worked with the development and manufacturing engineers at IBM’s East Fishkill plant to bring electrochemistry into their production line.

A Quality Metric for Defect Inspection Recipes

This paper describes a metric that measures the quality of defect inspection recipes. It takes into account several factors including nonvisual rate, defect of interest rate, defect count per wafer, and inspection time. The calculation runs automatically, and only minimal user input is necessary. Different weighting models allow giving each factor more or less importance, thus making the metric flexible for different applications in development and manufacturing. The result is a final score for each recipe. A list of inspection recipes can be sorted by scores to show that recipe needs optimization. Several examples show the use of the quality metric in IBM's East Fishkill development facility.

Improvement of Back-Side Cosmetic Defects And Wafer Strength

The continued challenge to keep up with Moore's law with aggressive device scaling, and shrinking wiring dimensions established perpetual need for novel materials and dictates ever tighter semiconductor process fidelity. Despite large progress with reducing defect densities on the device side of Si wafers, considerably less attention is being paid to the wafer back-side. Back-side wafer defects have been shown to reduce yield by leading to die breakage during packaging processes. Scratches and voids formed on the back-side of the wafer during various manufacturing processes have been shown to create weak spots on the wafer, which can act as initiation points for die crack formation and propagation. In this paper, we present the technical details of a back-side wet etch clean process which helps reducing back-side defect densities significantly. The process is set up on a single wafer wet etch tool at IBM's East Fishkill 300 mm wafer fabrication facility. The process removes the outer back-side layer of the silicon wafer which has become defective and damaged as a result of previous processing steps. This new defect removal process increases die strength, which is measured as wafer mechanical strength, and removes surface defects from the back-side of the wafer. Our results show that removal of 15–30 microns from the wafer back-side reduces the amount of cosmetic defects on the back-side of the wafer by 90%, while increasing die strength by 60%. The effects of the back-side wet etch clean process on the wafer optical appearance and mechanical properties were characterized, and supporting data such as atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), defect inspection, thermal interface material adhesion test, and die strength is included. Results from package level modules indicate an increase in reliability compared to the uncleaned Si back-side. It can be concluded that wet Si removal process described in this paper is a viable method to reduce the back-side defect density with an associated increase in final module product yield.

What We Learned and Used in the First Inductively Coupled Plasma for Plasma Processing and in Later Development

The first inductively coupled plasmas (ICPs) for plasma processing, also called radio frequency induction (RFI), were developed at IBM, East Fishkill, NY, U.S.A. These were extremely efficient at producing high density plasma. This paper will discuss: 1) How to drive the antenna to get high plasma density with low plasma voltage and low capacitively coupled plasma (CCP) losses, 2) low matching losses, 3) the optimum way (presets) to start an ICP, 4) frequency effects, and 5) achieving high plasma stability.

Process Window Centering for 22 nm Lithography

Process window centering (PWC) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between focus exposure matrix, where centering is based only on critical dimension measurements of a few specific structures and process window qualification which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBM's Albany, NY, and East Fishkill, NY, development facilities using KLA-Tencor's 28xx brightfield defect inspection system.

Experiences in implementing simulation-based support for operational decision making in semiconductor manufacturing

We describe a discrete event simulator that has been deployed in a 300 mm wafer fabrication plant to aid short-term, operational decision-making. Our simulator has been designed and calibrated to produce reliable predictions over simulation horizons as short as a few days to several weeks. It has been automated to run daily, without the need for manually provided data. We provide motivating examples illustrating the need for short-term predictions, and share insights on aspects of the simulator design that contribute to its usefulness and accuracy. Finally, we include several examples of how the simulator has been used to aid operational and tactical decision-making at the IBM wafer fabrication plant in East Fishkill, NY.

Contributors

Contributors

Queueing Model Improves IBM's Semiconductor Capacity and Lead-Time Management

At IBM's 300 mm semiconductor plant in East Fishkill, New York, we developed and implemented the Enterprise Production Planning and Optimization System (EPOS), an advanced queueing network model for capacity planning. EPOS extends earlier queueing network models by adding the ability to model product-specific batch service and batch arrivals and multichamber process equipment, and by embedding a linear program for allocating lots to the right queues when route choices are present. EPOS addresses both short-term tactical capacity planning and long-term strategic capital investment planning. It has become an integral part of predicting factory bottlenecks, prioritizing continuous-improvement efforts, planning capital equipment investments, and managing factory lead times. EPOS results have guided IBM's efforts to improve factory performance and reduce tens of millions of dollars of expense.

Milestones in a Quarter Century of CMP - Plenary

A quarter century has passed since the first semiconductor planarization experiments were conducted in the silicon wafer manufacturing facility in 1983 at IBM in East Fishkill, NY. This paper will review selected highlights of the technology and business drivers that shaped what has become a pervasive, critically enabling process sector in the pursuit of Moore's Law. Since 1988 the segment has grown from zero to $1.2B in capital equipment and $2.0B in consumable materials and ancillaries annually. The fundamental CMP process consisting of a polisher, slurry and pad has spawned a supply chain of no fewer than 18 uniquely identifiable CMP-related product lines and countless businesses. CMP has indeed matured, with an overall growth rate that matches but no longer exceeds that of the industry to which it has become so vital. The paper will conclude with an outlook for the near-term growth opportunities for CMP.

Crystallographic Texture and Phase Metrology During Damascene Copper Processing

AbstractThe rapid adoption of damascene copper technology has brought about an increased need to understand and control microstructure in the barrier and metal layers during processing. We have developed and implemented a methodology for rapidly characterizing thin film polycrystalline microstructures on 200 mm Si substrates using an X-ray diffraction (XRD) based metrology tool to measure crystallographic texture and phase in a time frame suitable for in-line applications. The acquired data can be used as a direct measure of the deposition process in terms of film quality, reproducibility and stability over time. The spatial distribution of crystallographic texture and phase can be measured on a single wafer in order to check within wafer uniformity. These same measurements can also be carried out at predetermined intervals on wafers from single deposition tools, with the results used to create a database that can be applied to process control trend charting and to the establishment of acceptance criteria. The methodology developed makes use of several novel data analysis and collection techniques, such as the use of a direct matrix transformation method to determine the orientation distribution function (ODF) from a group of truncated pole figures. Useful quantitative outputs of the ODF, such as volumetric fractions of crystallographic texture components, can be used in quantifying texture evolution within and between wafers. On-the-fly texture compensation can also be used to generate useful quantitative phase and film thickness measurements. We present the principles of operation of this metrology tool and selected examples collected in the IBM's Advanced Semiconductor Technology Center (ASTC), East Fishkill, NY.

PREVAIL-EPL alpha tool: Early results

The IBM/Nikon alliance is developing an EPL stepper alpha tool based on the PREVAIL technology. This article provides a status report on the alliance activity with particular focus on the electron optical subsystem developed at IBM. We have previously described design features of the PREVAIL Alpha system. The state-of-the-art e-beam lithography concepts have since been reduced to practice and turned into functional building blocks of a production level lithography tool. The electron optical subsystem has been designed, built, assembled, and tested at IBM’s Semiconductor Research and Development Center (SRDC) in East Fishkill, NY. After demonstrating subsystem functionality, the column, an interim mechanical system and all associated control electronics hardware and software have been shipped during January 2001 to Nikon’s facility in Kumagaya, Japan, for integration into the Nikon commercial e-beam stepper Alpha tool. Postshipment activity has been directed primarily toward demonstrating subfield stitching, a task which exercises system architecture, calibration, stability, and noise performance.

Fixed Abrasive Technology for STI CMP on a Web Format Tool

ABSTRACTShallow trench isolation (STI) requires a high quality oxide with superior fill capability provided by High Density Plasma (HDP) oxide. Unfortunately, the HDP deposition process can create large within die topographies that are difficult to polish directly using conventional silica slurries. As a result, etch back integration schemes have traditionally been incorporated for STI polish. A more revolutionary approach is the use of Fixed Abrasive (FA) CMP [1]. FA CMP allows direct STI polish with good planarization/process stability, eliminating the need for prior etch back. The planarization efficiency is strongly dependent on the shape of the pad composites that hold the CeO2 mineral. Fixed abrasive pads with pyramid and pole shapes are available. In this work, three different fixed abrasive pads supplied by 3M corporation were evaluated for STI CMP polish performance using the Obsidian 8200C web format CMP tool. Basic polish characteristics such as planarity (dependence on sub-pad/pattern density), selectivity to topography, oxide dishing and nitride erosion are presented. The FA pads discussed here have been classified as “slow”, “medium” or “fast” depending on blanket oxide removal rate.The slow rate pad had a very high selectivity to topography and very low dishing of the down area oxide. The removal rate of blanket oxide was less than 100 Å/min. The pad was best suited to the polish of isolation trench structures with small, controlled overfill (> 200 Å) across the wafer. A large process window was demonstrated. The removal rate of the “medium” pad also decreased significantly at the onset of planarization with a blanket oxide removal rate of ca. 200 Å/min. Unlike the slow rate pad, the medium rate pad did not provide a suitable overpolish process window required for a manufacturable STI process. It is believed this pad would be a good choice for BPSG polish. In contrast to the slow and medium rate pads, the blanket oxide removal rate of the fast pad was ca. 2000 Å/min with no self-stopping capability at the onset of planarization. The removal rate was extremely center fast, such that it could not be compensated by adjustment of tool parameters. Use of a modified process developed within the DRAM development alliance (DDA) at East Fishkill (IBM/ Infineon) enabled the fast pad to polish deep STI structures that would otherwise be impossible using the slow or medium rate pads.

PREVAIL Alpha system: Status and design considerations

An overview is given of the PREVAIL Alpha system program, a joint project of IBM and Nikon to develop a production-level electron project lithography system. The Alpha system program is based on the successful completion of an initial feasibility phase conducted by the IBM/Nikon alliance team and on the PREVAIL proof of concept results reported at EIPBN 1999. The electron beam column and associated electronics and software are under development at IBM’s Semiconductor R&D Center in East Fishkill, New York, while the high speed, high precision stages for both reticle and wafer as well as the overall systems architecture are being developed at Nikon’s facilities. A key architectural objective is the combination of leading edge stepper technology with state-of-the-art PREVAIL electron optics. The design of the electron optics is based on carefully balancing geometric aberrations and Coulomb interactions for optimum resolution at the required high beam current. Cornerstones of the design are the high emittance gun and the curvilinear variable axis lens concept developed for PREVAIL. Design considerations of the Alpha column are emphasized including a detailed treatment of space-charge lens aberrations.

Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies

Total-dose and single-event-effect radiation characterization of 0.25 micron test macro SRAMs fabricated at IBM's East Fishkill research foundry in un-hardened bulk and un-hardened partially-depleted SOI silicon, are reported. The design and fabrication process were optimized for high-performance and short access time using supply voltages of 2.5 V for the 64 K-bit and 1.8 V for the 144 K and 288 K-bit test macro SRAMs.

Large format fabrication-a practical approach to low cost MCM-D

The IBM Microelectronics Division at East Fishkill has recently demonstrated the fabrication of thin films for MCM-D on large area panels, 300 mm/spl times/300 mm in size. Fabrication of the thin films was accomplished on IBM's 300 mm development line using immersion development of photosensitive polyimide for via formation and electrolytic plating to define wiring and terminal metal levels. One plane pair of thin films was constructed on Corning glass 7059 panels for 35 /spl mu/m lines on 85 /spl mu/m pitch. In addition, two metal-dielectric levels with 13 /spl mu/m lines on 25 /spl mu/m pitch have also been demonstrated. The 25 /spl mu/m pitch represents the most aggressive groundrule practised in electronic packaging today. The successful production of electrically good substrates at a high yield from a 300 mm panel provides a gateway to significant cost reductions of future MCM-D products. This paper discusses the processes and equipment used to fabricate two different test vehicles, as well as some of the cost and yield considerations associated with large area panel processing for MCM-D packages. >

Operating experience with the Helios compact storage ring at IBM

Helios is a compact, superconducting storage ring designed and manufactured by Oxford Instruments specifically for use as an X-ray source for lithography. The ring, which runs at 686 MeV and has a critical wavelength of λ c = 9 A ̊ , uses a 200 MeV linac for injection. The ring was delivered to the IBM Advanced Lithography Facility in East Fishkill, New York in the spring of 1991 and has been in routine use since the beginning of 1992. Its performance has been characterized from both technical (beam size, lifetime, etc.) and functional (reliability, ease of use, etc.) standpoints. The specifications for the storage ring are reviewed with an emphasis on their relation to lithographic requirements. The ring has met and in some cases significantly exceeded the original specifications, having an average stored current of ∼ 165 mA with a 1/e lifetime of ∼ 20 hours at a current of 200 mA. Re-injection typically takes 15–20 min. Beam has been available more than 95% of the scheduled time since January 1992, which is particularly significant for a tool considered for use in a manufacturing application. This paper discusses the operating history of the ring, describing the improvements that have been achieved in such areas as beam lifetime, reliability, and injection, including the commissioning of a low energy (90 MeV) injection mode. The present performance of the ring is also summarized.

Performance of a wide-field flux delivery system for synchrotron x-ray lithography

An x-ray flux delivery system consisting of a compact storage ring and dedicated beamlines is now in routine use in the IBM Advanced Lithography Facility in East Fishkill, New York. The beamlines have been designed for use with a stepper that scans the mask and wafer vertically through a stationary beam. The performance of the system from a lithographic standpoint is reported. The measured size and stability of the synchrotron x-ray source will be presented, and the design and performance of the beamlines will be discussed. The beamlines have been designed to provide high intensity, uniform illumination over a wide field. The overall performance of the system has been evaluated by measuring the flux at the mask plane in the stepper. A horizontal uniformity of better than ±2% over a field more than 50 mm wide has been achieved; the vertical uniformity is limited by the uniformity of the stepper scanning mechanism. The delivered mask-incident flux per milliampere of stored beam current has been found to be 1.5 mW/(mA cm), approximately four times greater than obtained with a simple planar mirror. A 100 mJ/cm2 resist with a mask transmission of 50% therefore requires a less than 2 s exposure (plus overscan overhead) for a 2.5 cm high field at a typical stored current of 200 mA, independent of the field width (up to the maximum of more than 50 mm). In addition, the source has proved itself to be highly reliable, with beam available for 99% of the scheduled time over the most recent seven month period.

X-ray lithography in IBM, 1980–1992, the development years

The IBM X-ray lithography research and development program is outlined, from a personal perspective, covering the period from the inception of the program in 1980 through the development of IBM's own storage ring for X-ray production in 1992. The following aspects, among others, are discussed: origins of the program; acquisition of an X-ray port at Brookhaven National Laboratory; masks for X-ray lithography; development of special tooling for X-ray lithography, including a wafer stepper, a precision e-beam X-ray mask writing system, and a superconducting (dipole) electron synchrotron installed in the IBM Advanced Lithography Facility (ALF) in East Fishkill, New York. Key device programs were conducted to increase understanding of the X-ray lithography process and confirm its utility.

Performance of the IBM synchrotron X-ray source for lithography

The compact superconducting synchrotron X-ray source at the IBM Advanced Lithography Facility in East Fishkill, New York has been in service to customers since the start of 1992. Its availability during scheduled time is greater than 90%, with recent months frequently surpassing 95%. Data on the long-term behavior of the X-ray source properties and subsystem performance are now available. The full system continues to meet all specifications and even to surpass them in key areas. Measured electron beam properties such as beam size, short- and long-term positional stability, and beam lifetime are presented. Lifetimes greater than 20 hours for typical stored beams have significantly simplified operations and increased availability compared to projections. This paper also describes some unique features of this X-ray source and goes beyond a discussion of downtime to describe the efforts behind the scenes to maintain and operate it.