Dynamic Voltage Stress Research Articles

Analysis of Degradation Mechanism in Poly-Si TFTs Under Dynamic Gate Voltage Stress With Short Pulse Width Duration

Analysis of Degradation Mechanism in Poly-Si TFTs Under Dynamic Gate Voltage Stress With Short Pulse Width Duration

Dynamic Time Evolutionary Aging Analysis for Device-Circuit Lifetime Estimation of Thin-Film Transistors

We present a new methodology to estimate the lifetime of thin-film-transistor (TFT)-based scan driver circuit in display application with the dynamic time evolutionary aging model. The proposed method not only enables more accurate device level estimation but also circuit level aging prediction given that the TFTs are stressed dynamically. To properly handle threshold voltage shift ( $\Delta \text{V}_{\text {th}}$ ) of each TFTs in the scan driver under dynamic voltage stress patterns like the alternative voltage level and frequency, a time discretization strategy considering the voltage bias stress feedback is developed to be adaptable with SPICE transient simulation simply. The results show that $\Delta \text{V}_{\text {th}}$ of each TFTs in scan driver circuit can be evolved in real time accordingly under dynamic stress. What’s more, an exponential relationship between the aging parameter $\beta $ and the aging time is for the first time obtained, which has much importance for predicting lifetime of scan driver and other TFT-based circuit.

Surface Spiral Parallel and Antiparallel Winding Designs for High Efficiency, Low Spatial Voltage Stress, and Inductive Wireless Power Transfer Systems

Surface spiral winding (SSW) has been demonstrated to achieve low skin and proximity effects copper losses, and low air-gap magnetic flux density in MHz, kW level inductive wireless power transfer systems. The dielectric losses are still the limiting factor to further improve the coil-to-coil efficiency. In addition, high spatial voltage stress between the first turn and the end turn limits the maximum transferable power due to the voltage breakdown. This paper develops alternative coil configurations to reduce the copper loss, the dielectric losses, and the spatial voltage stress. Through emulating SSW using copper tubing, the dielectric losses and the spatial electric field between adjacent turns are reduced simultaneously. Two surface spiral parallel winding designs are proposed to reduce the equivalent series resistance and improve the coil-to-coil transfer efficiency. A surface spiral antiparallel winding design is proposed to equalize dynamic voltage stress between adjacent turns and improve power scalability while maintaining high coil-to-coil transfer efficiency.

Endurance of magnetic tunnel junctions under dynamic voltage stress

MgAl2O4 (MAO)-based magnetic tunnel junctions (MTJs) with an MAO thickness of ∼1.25 nm are fabricated and their cycling characteristics under dynamic voltage stress are evaluated. The speed of breakdown strongly depended on the pulse polarities used, bipolar, positive (+) unipolar, and negative (−) unipolar. The bipolar condition yielded more rapid breakdown under cycling. Between the two unipolar conditions, positive bias yielded more rapid breakdown than negative bias; the difference between these is understood to arise from the conditions of the interface between the MAO and ferromagnetic layers. Among apparently normal MTJ cells showing little resistance drift, 20% were degraded during a long cycling test in the bipolar stress condition. Thus, the use of bipolar voltage stress is essential to screen for potentially defective MTJs, and the asymmetric condition at the interface is minimised by process control for application of the simple unipolar bias condition.

A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> metal-insulator-metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of α as a function of stress time under constant voltage stress (CVS) gradually decreased. Moreover, ΔC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stress</sub> /C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> under dynamic voltage stress was much greater than under CVS, which indicates that new defects and charge trapping could be generated in high-κ (HK) dielectric under dynamic voltage stress under negative voltage as well as positive voltage. The extracted average value of the Weibull slope (β) at 125°C was in the range 1.3-1.6. The average field acceleration parameter was ~8.67 cm/MV, and an effective dipole moment of bond breakage peff was ~29.73e Å. The thermochemical model (E model) suggested that the oxygen vacancies induced by the dipolar energy contribution (p · Eloc) easily caused bond breakage in the HK dielectric. The energy required to form another V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> was weakened to the bond strength of polar molecules. The characteristic breakdown strength (EBD) of ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> was 6.31 MV/cm, and the extracted activation energy AH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> * was 1.874 eV when considering E model.

Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures

1200 V Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) have been characterized at high operational temperatures. For packaged JFETs obtained from a collaborating manufacturer, the threshold shift (ΔVT) was measured under both static and dynamic voltage stress and, in all cases, was less than 2 mV, which is within the measurement margin of error. Temperatures up to 250°C and stress times as long as 200 hours were evaluated. As a comparison, commercially available SiC MOSFETs demonstrated shifts of up to 300 mV after 30 minutes of static gate stress at 175°C. In addition, results from unpackaged JFET die at temperatures up to 525°C show ΔVT values of less than 10 mV for all stress conditions. Although VT remained unchanged for the duration of the test for both static and dynamic stress conditions, under dynamic stress conditions the JFET packaged parts demonstrated a linear increase in sub-threshold leakage current of around 15.6 nA per hour; in contrast, the MOSFET devices showed an exponential increase in sub-threshold leakage under dynamic stress. The increase in sub-threshold leakage current could be recovered temporarily, but long-term behavior was consistent with cumulative damage.

Charge Trapping Characteristics of TaYOx Gate Dielectrics on Ge under DC and AC Stressing

TaYOx gate dielectric has been deposited on p-Ge by RF co-sputtering of Ta2O5 and Y2O3 targets. Charge trapping/detrapping behavior of Au/TaYOx/p-Ge MIS capacitors have been studied under DC and AC stressing of different amplitudes and dynamic voltage stresses in order to study the transient response and the degradation mechanism of the dielectric. The current transients observed during dynamic voltage stress have been interpreted in terms of the charging/discharging of Ge/TaYOx interface and bulk TaYOx traps. The change in Vfb and gate current during unipolar pulse voltage stressing shows that the main degradation takes place at low frequencies. Both types of trapping are observed under dynamic stressing both with the gate and substrate injections.

Thermal analysis on the degradation of poly-silicon TFTs under AC stress

In this work, the degradation mechanism of N-channel poly-silicon thin-film transistor (poly-Si TFT) has been investigated under dynamic voltage stress at room temperature. The ON-current of TFT is degraded to as low as 0.3 times of the initial value after 1000 s stress. On the other hand, both the sub-threshold swing and threshold voltage kept well during the AC stress. The current crowding effect was rapidly increased with increasing of stress duration. However, comparing the initial and degraded characteristics at rising temperature, namely, 150 °C, the ON-current of TFT only decrease to 75% of the initial value after 1000 s AC stress. It depicts that creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. At high temperature, electron has enough energy to pass the energy barrier created by ac stress and the degradation is less obvious.

Reliability of Ti-based Gate Dielectrics on strained-Si0.91Ge0.09 and Ge under Dynamic and AC Stressing

The trapped charge distributions in Al/TiO2/GeOxNy/p-Ge and Al/ TiO2/SiOxNy/strained-Si0.91Ge0.09 structures subjected dynamic stress of different amplitude and frequency in order to analyze the transient response and the degradation of the oxide as a function of different stress condition. The current transients and voltage transient observed in dynamic voltage (-4V to -9V) and current stresses (-2.5mA/cm2 to -12.5mA/cm2) have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar voltage stresses shows the degradation being much faster at low frequencies than at high frequencies.

Reliability assessment of SiO 2/ZrO 2 stack gate dielectric on strained-Si/Si 0.8Ge 0.2 heterolayers under dynamic and AC stress

The reliability characteristics of SiO 2/ZrO 2 gate dielectric stacks on strained-Si/Si 0.8Ge 0.2 have been investigated under dynamic and pulsed voltage stresses of different amplitude and frequency in order to analyze the transient response and the degradation of oxide as a function of stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar pulsed voltage stresses shows the degradation being much faster at low frequencies than at high frequencies. Results have been compared with those obtained after CVS, as a function of injected charge and pulse frequency.

Degradation of Laser-Crystallized Laterally Grown Poly-Si TFT under Dynamic Stress

This letter studies the electrical degradation of laterally grown polycrystalline silicon thin-film transistors (poly-Si TFTs) under dynamic voltage stress. The experimental results show the serious electrical degradation of poly-Si TFTs with a protruding grain boundary. The concentration of the electric field in the protrusion region was verified by capacitance-voltage measurements and simulation of the device characteristics. These results reveal that more electrons are induced at the grain boundary of the poly-Si channel because of the relatively high electric field in the protrusion region. Based on these data, this letter proposes a model to explain the enhanced electrical degradation of poly-Si TFTs with a protruding grain boundary, generated by laser-crystallized lateral growth technique

Dynamic voltage stress effects on nMOS varactor

The degradations in the nMOS device due to high-frequency (900 MHz) dynamic stress are shown experimentally. The stress-induced shifts in DC and larger-signal C-V characteristics are presented. Although the high-frequency stress-induced degradations are much smaller than DC stress, the effects on C-V curves and quality factor cannot be neglected. An nMOS LC oscillator, wherein the varactor is operated under the same dynamic bias conditions as in the stress experiment, has been evaluated through Cadence Spectre simulation. The performance of the LC oscillator degrades significantly due to the dynamic stress.

Dynamic stress-induced high-frequency noise degradations in nMOSFETs

Device parameter shifts in nMOSFETs subject to inverter-like dynamic voltage stress are examined experimentally. Model equations to relate high-frequency noise to device parameters are given. Dynamic stress-induced degradations in high-frequency noise performance of 0.16 μm nMOSFETs are investigated. Good agreement between the analytical predictions and experimental data is obtained. Noise performance of a Gilbert mixer is evaluated using Cadence SpectreRF simulation with the measured device model parameters.

MOS RF Reliability Subject to Dynamic Voltage Stress—Modeling and Analysis

Dynamic stress on MOSFETs with 900-MHz inverter-like waveforms as well as static (or dc) stress were evaluated experimentally. It showed that the degradation due to dynamic stress is less than that of dc stress for our test transistors. A compact model is used to evaluate the degradation in radio frequency performances, such as transconductance, cutoff frequency, linearity, and noise figure. A class-AB power amplifier is presented as an example to demonstrate the effect of dynamic stress on RF circuit performance.

Multi-level voltage reinjection-a new concept in high voltage source conversion

A voltage source converter is proposed, in which the multi-step output voltage waveform is achieved by the reinjection of different DC voltage levels via the common neutral point of the converter bridges. The number of clamping switches are substantially reduced, permitting the use of higher level numbers to achieve very low distortion without the assistance of PWM. The reinjection concept causes the voltage across the main bridges to vary in step waveforms and the commutations in the main valves to occur at zero voltage, with considerably reduced dynamic voltage stress and switching losses.

Degradation and breakdown of thin silicon dioxide films under dynamic electrical stress

Thin oxide MOS capacitors have been subjected to dynamic voltage stresses of different characteristics (shape, amplitude and frequency) in order to analyze the transient response and the degradation of the oxide as a function of the stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. As for the oxide degradation, the experimental data has been interpreted in terms of a phenomenological model previously developed for dc stresses. According to this model, the current evolution in voltage stresses is assumed to be related to the oxide wearout. The evolution of the current during bipolar voltage stresses shows the existence of two different regimes, the degradation being much faster at low frequencies than at high frequencies. In both regimes, the frequency dependence is not significant, and the change from one regime to the other takes place at a threshold frequency which depends on the oxide field. These trends are also observed in time-to-breakdown versus frequency data, thus suggesting a strong correlation between degradation and breakdown in dynamic stresses. The experimental results are discussed in terms of microscopic degradation models.

High field dynamic stress of thin SiO 2 films

Thin-oxide MOS capacitors are subjected to unipolar and bipolar dynamic voltage stresses. The characteristic times of the measured current transients indicate that they are due to changes in the occupancy of interface states. A reasonable picture is presented which invokes the restoration of equilibrium at the oxide/semiconductor interfaces, and the stripping of electrons by Fowler-Nordheim tunnelling when the applied field is very high. On the other hand, time-to-breakdown data show that, in agreement with the results of other authors, oxide reliability is considerably higher under high frequency bipolar stresses. A smaller dependence of time-to-breakdown on the frequency of unipolar stresses is also found, and is qualitatively interpreted in terms of the average energy required to breakdown.

The statistics of dielectric breakdown in MOS capacitors under static and dynamic voltage stress

The statistics of dielectric breakdown at fields ⩾ 8 MV/cm has been studied under both static (constant voltage) and dynamic (ramped voltage) conditions. MOS capacitors of the same size and from the same wafer were used for all measurements. Data from both types of test conformed to a Weibull distribution. The Weibull parameters a and b, which determine the time and field dependence of breakdown, were calculated from static tests at various applied fields and independently from dynamic tests at various ramp-rates. The values of a and b were: a ⋍ 0.24; b ⋍ 6.89 and a ⋍ 0.34; b ⋍ 6.55, from static and dynamic tests respectively. The similarity of the values for the two pairs of Weibull parameters suggests that breakdown proceeds by the same mechanism in both types of test.