Dynamic Voltage Scaling Technique Research Articles

System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems

System optimization techniques are widely used to improve energy efficiency as well as overall performance. Dynamic voltage scaling (DVS) is well studied and known to be successful in reducing processor energy consumption. Due to the increasing significance of the memory subsystem's energy consumption, dynamic cache reconfiguration (DCR) techniques are recently proposed at the aim of improving cache subsystem's energy efficiency. As the manufacturing technology scales into the order of nanometers, leakage current, which leads to static power consumption, becomes a significant contributor in the overall power dissipation. In this paper, we consider various system components and study their impact on system-wide energy consumption under different processor voltage levels as well as cache configurations. Based on the observation, we efficiently integrate DVS and DCR techniques together to make decisions judiciously so that the total energy consumption is minimized. Our studies show that considering only DVS or DCR and ignoring the impact from other system components may lead to incorrect conclusions in overall energy savings. Experimental results demonstrate that our approach outperforms existing leakage-aware DVS techniques by 47.6% and leakage-oblivious DVS + DCR technique by up to 23.5%.

Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling

Dynamic voltage scaling (DVS) is one of the most effective techniques for reducing energy consumption on battery-operated embedded systems. According to the granularity of units to which voltage scaling is applied, the DVS problem can be divided into two subproblems: (i) inter-task DVS problem and (ii) intra-task DVS problem. A lot of effective DVS techniques have addressed either one of the two subproblems, but none of them have attempted to solve both simultaneously. This paper examines the problem of combined inter-and intra-task DVS, called the combined DVS (CDVS) problem. We solve the CDVS problem in two embedded system domains: one is systems with a sleep state and the other without sleep state. For systems without sleep state, we propose a close-to-optimal algorithm for the CDVS problem. We show that the algorithm is optimal when the power is a quadratically increasing function of the system's clock speed or the applied voltage level. For systems with a sleep state, we propose a refinement algorithm that fine-tunes the solution to the CDVS problem without sleep state to further reduce energy consumption by exploiting sleep state. Experimental results show that our proposed CDVS algorithm without sleep state is able to reduce the energy consumption by 12.5% on average over the results by the method that sequentially performs two existing inter-and intra-task DVS techniques, which are both optimal under no sleep state. Furthermore, our CDVS algorithm with a sleep state can reduce the energy consumption by 7.1% on average over the results by the conventional representative method that utilizes sleep state, but does not consider intra-and inter-task DVS simultaneously.

TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems

Due to the increasing chip temperature and the strong dependency of leakage power on temperature, thermal aware power management has received a considerable amount of attention recently in energy efficient system design. In this paper, we propose a temperature-aware intra-task scheduling algorithm to minimize leakage energy in real-time systems. The basic idea of our algorithm is to run tasks at full speed when the chip temperature is low or the work urgency is high, and switch the processor to a low-power state when the chip temperature is high or the workload is light. Our offline algorithm can achieve the optimal leakage reduction for a given task with the worst-case execution time, while the online algorithm has a very low runtime complexity. The simulation results show that the online algorithm is able to reduce 34% of total leakage energy on average in both real-world and artificial benchmarks. Finally, we demonstrate how to combine our algorithm with existing dynamic voltage scaling technique to optimize the overall energy consumption.

Energy-aware job scheduler for high-performance computing

In recent years energy-aware computing has become a major topic, not only in wireless and mobile devices but also in devices using wired technology. The ICT industry is consuming an increasing amount of energy and a large part of the consumption is generated by large-scale data centers. In High-Performance Computing (HPC) data centers, higher performance equals higher energy consumption. This has created incentives on exploring several alternatives to reduce the energy consumption of the system, such as energy-efficient hardware or the Dynamic Voltage and Frequency Scaling (DVFS) technique. This work presents an energy-aware scheduler that can be applied to a HPC data center without any changes in hardware. The scheduler is evaluated with a simulation model and a real-world HPC testbed. Our experiments indicate that the scheduler is able to reduce the energy consumption by 6---16% depending on the job workload. More importantly, there is no significant slowdown in the turnaround time or increase in the wait time of the job. The results hereby evidence that our approach can be beneficial for HPC data center operators without a large penalty on service level agreements.

System-wide energy optimization for multiple DVS components and real-time tasks

Most dynamic voltage and frequency scaling (DVS) techniques adjust only CPU parameters; however, recent embedded systems provide multiple adjustable clocks which can be independently tuned. When considering multiple components, energy optimal frequencies depend on task set characteristics such as the number of CPU and memory access cycles. In this work, we propose a realistic energy model considering multiple components with individually adjustable frequencies such as CPUs, system bus and memory, and related task set characteristics. The model is validated on a real platform and shows less than 2% relative error compared to measured values. Based on the proposed energy model, we present an optimal static frequency assignment scheme for multiple DVS components to schedule a set of periodic real-time tasks. We simulate the energy gain of the proposed scheme compared to other DVS schemes for various task and system configurations, showing up to a 20% energy reduction. We also experimentally verify energy savings of the proposed scheme on a real hardware platform.

Energy Efficient Block-Partitioned Multicore Processors for Parallel Applications

Due to the increasing power consumption in modern computing systems, energy management has become an important research area in the last decade. Recently, multicore has emerged to be an energy efficient architecture that exploits parallelisms in modern applications. However, as the number of cores on a single chip continues to increase, it has been a grand challenge on how to effectively manage the energy efficiency of multicore-based systems. In this paper, based on the voltage island and dynamic voltage and frequency scaling (DVFS) techniques, we investigate the energy efficiency of block-partitioned multicore processors, where cores are grouped into blocks with the cores on one block sharing a DVFSenabled power supply. Depending on the number of cores on each block, we study both symmetric and asymmetric block configurations. We develop a system-level power model (which can support various power management techniques) and derive both block- and system-wide energy-efficient frequencies for systems with block-partitioned multicore processors. Based on the power model, we prove that, for embarrassingly parallel applications, having all cores on a single block can achieve the same energy savings as that of the individual block configuration (where each core forms a single block and has its own power supply). However, for applications with limited degrees of parallelism, we show the superiority of the buddy-asymmetric block configuration, where the number of required blocks (and power supplies) is logarithmically related to the number of cores on the chip, in that it can achieve the same amount of energy savings as that of the individual block configuration. The energy efficiency of different block configurations is further evaluated through extensive simulations with both synthetic as well as a real life application.

Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems

System optimization techniques based on dynamic reconfiguration are widely adopted for energy conservation. While dynamic voltage scaling (DVS) techniques have been extensively studied for processor energy conservation, dynamic cache reconfiguration (DCR) for reducing cache energy consumption in multitasking systems is still in its infancy. In this paper, we propose a general and flexible algorithm for energy optimization based on dynamic reconfiguration in multitasking systems. Our algorithm is flexibly parameterized and can be used to provide tradeoffs between running time and solution quality. Furthermore, it can easily incorporate variable reconfiguration overhead. Experimental results show that our technique can generate near-optimal solutions with significantly low running time and memory requirements.

Energy efficient scheduling for real-time embedded systems with QoS guarantee

While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for the overall energy re...

A New Energy-Aware Dynamic Task Set Partitioning Algorithm for Soft and Hard Embedded Real-Time Systems

Power consumption is a major design concern in current embedded systems. To deal with consumption, many systems apply dynamic voltage scaling (DVS) techniques which dynamically change the system speed depending on the workload characteristics. DVS costs in a multicore system can be reduced by sharing the same DVS regulator among the cores. In this context, to handle energy efficiently, the workload must be properly balanced among the cores. This paper proposes a new heuristic algorithm to balance the workload in an embedded system with a coarse-grain multithreaded multicore processor. This heuristic is aimed at improving the overlapping time between the memory and the processor while keeping balanced core utilizations. To this end, the heuristic dynamically drives the frequency/voltage level to guarantee deadline fulfillment of the hard real-time tasks as well as to achieve a good trade-off between deadline losses and energy savings of the soft real-time tasks. The proposed technique has been evaluated on a model of a contemporary high-end ARM embedded microprocessor executing a set of standard embedded benchmarks. Energy savings depend on the range of frequency/voltage levels that the DVS regulator implements. Experimental results show that with the proposed heuristic, when working with hard real-time tasks, the energy consumption is about 33% the energy dissipated by a system without DVS regulator and balancing heuristic. Moreover, when soft real-time tasks are also considered, the normalized consumption presents values ranging in between 8 and 70% depending on the scheduler aggressiveness.

QoS-Sensitive Dynamic Voltage Scaling Algorithm for Wireless Multimedia Services

The past decade has seen a surge of research activities in the fields of mobile computing and wireless communication. In particular, recent technological advances have made portable devices, such as PDA, laptops, and wireless modems to be very compact and affordable. To effectively operate portable devices, energy efficiency and Quality of Service (QoS) provisioning are two primary concerns. Dynamic Voltage Scaling (DVS) is a common method for energy conservation for portable devices. However, due to the amount of data that needs to be dynamically handled in varying time periods, it is difficult to apply conventional DVS techniques to QoS sensitive multimedia applications. In this paper, a new adaptive DVS algorithm is proposed for QoS assurance and energy efficiency. Based on the repeated learning model, the proposed algorithm dynamically schedules multimedia service requests to strike the appropriate performance balance between contradictory requirements. Experimental results clearly indicate the performance of the proposed algorithm over that of existing schemes.

Dynamic Scheduling of Skippable Periodic Tasks With Energy Efficiency In Weakly Hard Real-Time System

Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between charges is an interesting challenge for system designers. Dynamic Voltage Scaling (DVS) allows a processor to dynamically change speed and voltage at run time, thereby saving energy by spreading run cycles into idle time. Knowing when to use full power and when not, requires the cooperation of the operating system scheduler. Usually, higher processor voltage and frequency leads to higher system throughput while energy reduction can be obtained using lower voltage and frequency. Instead of lowering processor voltage and frequency as much as possible, energy efficient real-time scheduling adjusts voltage and frequency according to some optimization criteria, such as low energy consumption or high throughput, while it meets the timing constraints of the real-time tasks. As the quantity and functional complexity of battery powered portable devices continues to raise, energy efficient design of such devices has become increasingly important. Many real-time scheduling algorithms have been developed recently to reduce energy consumption in the portable devices that use DVS capable processors. Extensive power aware scheduling techniques have been published for energy reduction, but most of them have been focused solely on reducing the processor energy consumption. While the processor is one of the major power hungry units in the system, other peripherals such as network interface card, memory banks, disks also consume significant amount of power. Dynamic Power Down (DPD) technique is used to reduce energy consumption by shutting down the processing unit and peripheral devices, when the system is idle. Three algorithms namely Red Tasks Only (RTO), Blue When Possible (BWP) and Red as Late as Possible (RLP) are proposed in the literature to schedule the real-time tasks in Weakly-hard real-time systems. This paper proposes optimal slack management algorithms to make the above existing weakly hard real-time scheduling algorithms energy efficient using DVS and DPD techniques.

Min-energy scheduling for aligned jobs in accelerate model

A dynamic voltage scaling technique provides the capability for processors to adjust the speed and control the energy consumption. We study the pessimistic accelerate model where the acceleration rate of the processor speed is at most K and jobs cannot be executed during the speed transition period. The objective is to find a min-energy (optimal) schedule that finishes every job within its deadline. The job set we study in this paper is aligned jobs where earlier released jobs have earlier deadlines. We start by investigating a special case where all jobs have a common arrival time and design an O ( n 2 ) algorithm to compute the optimal schedule based on some nice properties of the optimal schedule. Then, we study the general aligned jobs and obtain an O ( n 2 ) algorithm to compute the optimal schedule by using the algorithm for the common arrival time case as a building block. Because our algorithm relies on the computation of the optimal schedule in the ideal model ( K = ∞ ), in order to achieve O ( n 2 ) complexity, we improve the complexity of computing the optimal schedule in the ideal model for aligned jobs from the currently best known O ( n 2 log n ) to O ( n 2 ) .

Approximation algorithms for variable voltage processors: Min energy, max throughput and online heuristics

Dynamic Voltage Scaling techniques allow the processor to set its speed dynamically in order to reduce energy consumption. It was shown that if the processor can run at arbitrary speeds and uses power s α when running at speed s , the online heuristic AVR has a competitive ratio ( 2 α ) α / 2 . In this paper we first study the online heuristics for the discrete model where the processor can only run at d given speeds. We propose a method to transform online heuristic AVR to an online heuristic for the discrete model and prove a competitive ratio 2 α − 1 ( α − 1 ) α − 1 ( δ α − 1 ) α ( δ − 1 ) ( δ α − δ ) α − 1 + 1 , where δ is the maximum ratio between adjacent non-zero speed levels. We also prove that the analysis holds for a class of heuristics that satisfy certain natural properties. We further study the throughput maximization problem when there is an upper bound for the maximum speed. We propose a greedy algorithm with running time O ( n 2 log n ) and prove that the output schedule is a 3-approximation of the throughput and a ( α − 1 ) α − 1 ( 3 α − 1 ) α 2 α α ( 3 α − 1 − 1 ) α − 1 -approximation of the energy consumption.

On Maximizing Reliability of Real-Time Embedded Applications Under Hard Energy Constraint

The dynamic voltage and frequency scaling (DVFS) technique is the basis of numerous state-of-the-art energy management schemes proposed for real-time embedded systems. However, recent research has illustrated the alarmingly negative impact of DVFS on task and system reliability. In this paper, we consider the problem of assigning processing frequencies to a set of real-time tasks in order to maximize the overall reliability, under given time and energy constraints. First, under the frame-based task model, we formulate the problem as a nonlinear optimization problem and show how to obtain the static optimal solution. Then, we propose online (dynamic) algorithms that detect early completions and adjust the task frequencies at runtime, to improve overall reliability. Furthermore, we extend these solutions to the periodic task model, with both static and dynamic solutions. All our solutions ensure that all timing constraints are met while the cumulative energy consumption of tasks does not exceed the given energy budget. Our simulation results indicate that our algorithms perform comparably to a clairvoyant optimal scheduler that knows the exact workload in advance.

Design of Digital Tri-mode Adaptive-Output Buck–Boost Power Converter for Power-Efficient Integrated Systems

An integrated buck-boost converter with a tri-mode digital control is presented. It employs an adaptive step-up/down voltage conversion to enable a wide range of output voltage. This is beneficial to the ever-increasing electronic systems that employ dynamic voltage scaling (DVS) techniques for power-efficient operations. Three control modes are employed in the converter to operate jointly and seamlessly for performance optimization during the periods of start-up, steady state, and dynamic voltage/load transient states. To avoid latch-up problem and minimize leakage current, an automatic substrate switching circuit (ASSC) is introduced. The design was fabricated in a 0.35-?m digital CMOS N-well process, with a die area of 1.3 mm2. It precisely regulates an adaptively adjustable power output from 0.9 to 3.0 V. The maximum efficiency is 96.5%, which is measured at 0.9-V output and 45-mW load power. The efficiency remains above 50% over the entire 800-mW power range. The converter responds to a 45-mA load step transient change within 600 ns. The DVS tracking speed is 37 ?s/V for a 1-V step-down change and is 150 ?s/V for a 1-V step-up change. With a line regulation of 20.4 mV/V, the converter functions robustly when the input power source frequently varies between 1.6 and 3.3 V. The ASSC consumes only 88- ?W static power.

PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications

Energy efficiency is a major concern in modern high-performance computing system design. In the past few years, there has been mounting evidence that power usage limits system scale and computing density, and thus, ultimately system performance. However, despite the impact of power and energy on the computer systems community, few studies provide insight to where and how power is consumed on high-performance systems and applications. In previous work, we designed a framework called PowerPack that was the first tool to isolate the power consumption of devices including disks, memory, NICs, and processors in a high-performance cluster and correlate these measurements to application functions. In this work, we extend our framework to support systems with multicore, multiprocessor-based nodes, and then provide in-depth analyses of the energy consumption of parallel applications on clusters of these systems. These analyses include the impacts of chip multiprocessing on power and energy efficiency, and its interaction with application executions. In addition, we use PowerPack to study the power dynamics and energy efficiencies of dynamic voltage and frequency scaling (DVFS) techniques on clusters. Our experiments reveal conclusively how intelligent DVFS scheduling can enhance system energy efficiency while maintaining performance.

Coscheduling of processor voltage and control task period for energy-efficient control systems

The Dynamic Voltage Scaling (DVS) technique has been widely studied for energy-constrained real-time systems; however, its application to control systems has not been studied in a variety of aspects. This article presents a novel method to simultaneously schedule processor voltage and control-task periods online, considering energy-efficiency of control systems as a whole. A new performance index is proposed, which contains both control performance and processor energy terms. Then, an online scheduler assigning processor voltage and control-task periods that maximizes the performance index is proposed. The performance of the proposed scheduler under varying control workload is verified using MATLAB simulations and experiments on an actual DVS hardware platform.

An overview of achieving energy efficiency in on-chip networks

Due to the increasing bandwidth demand for the network-on-chip (NoC), interconnection networks become a dominant source of energy consumption in systems-on-chip (SoCs) and chip multi processors (CMPs). Therefore, energy efficient NoC is key to a successful SoC development. This paper presents an overview of different techniques to achieve energy efficiency at the different levels of NoC design including: a) component level where dynamic voltage scaling (DVS) and dynamic link shutdown (DLS) techniques are reviewed; b) circuit level, e.g., voltage swinging of signals; c) architectural level, where specialised tools, such as Wattch and Orion are discussed. We also summarise research on thermal optimisation issues. To the best of our knowledge, this is the first survey of recent research results on the area.

Energy-Aware Compilation for Embedded Processors with Technology Scaling Considerations

With scaling of technology feature sizes, the share of leakage in total energy consumption of digital systems is on the rise. Conventional dynamic voltage scaling (DVS) techniques fail to accurately address the impact of scaling on system energy consumption breakdown, and hence, are incapable of achieving energy efficient solutions in all technology nodes. To overcome this problem, we propose utilizing adaptive body biasing (ABB) to adjust transistors' threshold voltage at runtime. While ABB has intrinsic limitations with deep sub-micron scaling, we demonstrate that it can be favorably combined with DVS to reduce overall energy consumption down to 45 nm technology node. We develop a leakage-aware compilation methodology for embedded applications under hard or soft timing constraint. Our technique targets embedded processors with both DVS and ABB capabilities, and has the unique advantage of jointly optimizing active and leakage energy dissipation. Considering the delay and energy overhead of switching between operating modes of the processor and execution deadline constraints, our compiler improves the energy consumption of the generated code by average of 21.66% at 90 nm. While our technique's improvement in energy dissipation over conventional DVS is small (6.43%) at 130 nm, the average improvement continues to grow to 12.23%, 18.63% and 22.16% for 90 nm, 65 nm and 45 technology nodes, respectively. Extensive experiments validate the effectiveness of our approach, explore the involved trade-offs, and offer insights into future trends with respect to technology scaling.

Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Dynamic voltage scaling (DVS) is a popular energy-saving technique for real-time tasks. The effectiveness of DVS critically depends on the accuracy of workload estimation, since DVS exploits the slack or the difference between the deadline and execution time. Many existing DVS techniques are profile based and simply utilize the worst-case or average execution time without estimation. Several recent approaches recognize the importance of workload estimation and adopt statistical estimation techniques. However, these approaches still require extensive profiling to extract reliable workload statistics and furthermore cannot effectively handle time-varying workloads. Feedback-control-based adaptive algorithms have been proposed to handle such nonstationary workloads, but their results are often too sensitive to parameter selection. To overcome these limitations of existing approaches, we propose a novel workload estimation technique for DVS. This technique is based on the Kalman filter and can estimate the processing time of workloads in a robust and accurate manner by adaptively calibrating estimation error by feedback. We tested the proposed method with workloads of various characteristics extracted from eight MPEG video clips. To thoroughly evaluate the performance of our approach, we used both a cycle-accurate simulator and an XScale-based test board. Our simulation result demonstrates that the proposed technique outperforms the compared alternatives with respect to the ability to meet given timing and Quality of Service constraints. Furthermore, we found that the accuracy of our approach is almost comparable to the oracle accuracy achievable only by offline analysis. Experimental results indicate that using our approach can reduce energy consumption by 57.5% on average, only with negligible deadline miss ratio (DMR) around 6.1%. Moreover, the average of computational overheads for the proposed technique is just 0.3%, which is the minimum value compared to other methods. More importantly, the DMR of our method is bounded by 11.7% in the worst case, while those of other methods are twice or more than ours. </para>