Dynamic Voltage And Frequency Scaling Techniques Research Articles

Dynamic voltage and frequency scaling algorithm for fault-tolerant real-time systems

Many modern real-time systems (RTSs) are required to provide both fault tolerance and energy-efficiency in addition to their main objective to compute and deliver correct results within a specified period of time. Dynamic voltage and frequency scaling (DVFS) technique is known as one of the most effective low-energy technique for RTSs. However, most existing DVFS techniques only focus on minimizing energy consumption without taking the fault-tolerant capability of RTS into account. To solve this problem, in this paper we developed a new heuristic-based fault-tolerant dynamic voltage and frequency scaling (FT-DVFS) algorithm. The goal of the proposed algorithm is to find frequencies at which each task should be executed such that the energy consumed by the set of task is minimized. Beside energy minimization FT-DVFS algorithm has to meet all real-time requirements of individual tasks and to keep the system’s ability to tolerate transient faults via task re-execution. The simulation results show that the proposed approach could save a significant amount of energy while preserving the required level of system’s fault-tolerance capability when compared with the solutions obtained without energy-minimization.

영상 프레임 디코딩 복잡도 예측을 통한 DVFS 전력감소 방식

최근 영상 디코더 시스템에서 소모전력을 절감하기 위한 방안으로 DVFS (Dynamic Voltage and Frequency Scaling) 방식을 적용한 알고리즘 들이 제안되고 있다. 이에 저자들은 논문[1]에서 전력소모를 최소화할 수 있는 스케줄링 알고리즘을 제시하였다. 이 알고리즘은 수학적으로 최적의 결과를 보장하지만, 사전에 화면 당 디코딩 계산양을 알 수 있다는 조건이 만족하여야 한다. 그러나 실제응용에서 이 조건은 만족되기 어려운 경우가 종종 존재한다. 본 논문에서는 이 제약사항을 극복하는 방안으로, 프레임의 데이터크기로 프레임의 디코딩 계산양을 예측하는 기법에 기초한 수정된 알고리즘을 제안한다. 실제 영상에서 추출된 데이터를 이용한 결과, 계산양 예측 알고리즘은 평균적으로 90%이상의 정확도를 보였으며, 따라서 계산양 예측 기법과 임계점에서의 프래임 크기 20% 내외의 완충버퍼 마진을 적용한 수정한 알고리즘은 버퍼 고갈과 넘침이 일어나지 않으며, 최적알고리즘과 비교할 때 거의 동일한 성능 (1~2% 이하의 성능저하)을 보이는 것을 확인하였다. Recently, intensive research has been performed for reducing video decoder energy consumption, especially based on DVFS (Dynamic Voltage and Frequency Scaling) technique. Our previous work [1] has proposed the optimal DVFS algorithm for energy reduction in video decoders. In spite of the mathematical optimality of the algorithm, the precondition of known frame decoding cycle/complexity limits its application to some realistic scenarios. This paper overcomes this limitation by frame data size-based estimation of frame decoding complexity. The proposed decoding complexity estimation method shows over 90% accuracy. And with this estimation method and buffer underflow margin of around 20% of frame size, almost same power consumption reduction performance as the optimal algorithm can be achieved.

Application-Support Particle Filter for Dynamic Voltage Scaling of Multimedia Applications

Dynamic Voltage and Frequency Scaling (DVFS) is an effective low-power technique for real-time workloads. Its effectiveness critically depends on the accurate prediction of the task execution time. Many DVFS approaches have been proposed, but they are insufficient for highly nonstationary workloads. Several recent DVFS techniques adopted adaptive filters to improve accuracy. However, their improvement was rather limited, since they mainly focused on applying a filter framework to the target application without tuning it. We address this issue by proposing Particle Filter (PF)-based video decoders (MPEG2 and H.264) which exploit application-specific characteristics. More specifically, our PF-based video decoders utilize the size of each frame for the prediction of its decoding time. Compared to previous work, the PF is more suitable for our purpose, since it achieves higher prediction accuracy, even for highly nonstationary workloads such as H.264 clips. Our results show that the energy saved by the proposed approach is comparable to that of the ideal policy called oracle-DVFS, while the existing methods we tested were far inferior to oracle-DVFS in terms of H.264 video decoding. Additionally, when our method was used, only 0.40 and 6.88 percent of the frames missed their deadlines with negligible computational overhead for MPEG and H.264, respectively.

Adaptive fault-tolerant DVFS with dynamic online AVF prediction

Advances in silicon technology and shrinking the feature size to nanometer levels make random variations and low reliability of nano-devices the most important concern for fault-tolerant design. Design of reliable and fault-tolerant embedded processors is mostly based on developing techniques that compensate reliability shortcomings by adding hardware or software redundancy. The recently-proposed redundancy adding techniques are generally applied uniformly to all parts of a system and lead to heavy overheads and inefficiencies in terms of performance, power, and area. Efficient employment of non-uniform redundancy becomes possible when a quantitative analysis of a system behavior while encountering transient faults is provided. In this work, we present a quantitative analysis of the behavior of an embedded processor regarding transient faults and propose a new approach that accurately predicts the architecture vulnerability factor (AVF) in real-time. Another critical concern in design of new-silicon processors is power consumption issue. Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling both energy consumption and performance of a system. Since rate of radiation-induced transient faults depends on operating frequency and supply voltage, DVFS techniques are recently shown to have compromising effects on electronic system reliability. Therefore, ignoring the effects of voltage scaling on fault rate could considerably degrade the system reliability. Here, by exploiting the proposed online AVF prediction methodology and based on analytic derivation, we propose a reliability-aware adaptive dynamic voltage and frequency scaling (DVFS) approach in case study of Multi-Processor System on Chip (MPSoC) with Multiple Clock Domain (MCD) pipeline architectures in which the frequency and voltage are scaled by simultaneously considering all three of power consumption, reliability, and performance. Comparing to the traditional methods of reliability-aware DVFS systems, the proposed reliability-aware DVFS method yields 50% better power saving at the same reliability level.

Power management by load forecasting in web server clusters

The complexity and requirements of web applications are increasing in order to meet more sophisticated business models (web services and cloud computing, for instance). For this reason, characteristics such as performance, scalability and security are addressed in web server cluster design. Due to the rising energy costs and also to environmental concerns, energy consumption in this type of system has become a main issue. This paper shows energy consumption reduction techniques that use a load forecasting method, combined with DVFS (Dynamic Voltage and Frequency Scaling) and dynamic configuration techniques (turning servers on and off), in a soft real-time web server clustered environment. Our system promotes energy consumption reduction while maintaining user’s satisfaction with respect to request deadlines being met. The results obtained show that prediction capabilities increase the QoS (Quality of Service) of the system, while maintaining or improving the energy savings over state-of-the-art power management mechanisms. To validate this predictive policy, a web application running a real workload profile was deployed in an Apache server cluster testbed running Linux.

Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems

Power demand grows much faster than battery capacity in embedded systems. Dynamic voltage and frequency scaling (DVFS) has been shown to be extremely efficient to save energy due to the exponential dependence of power on voltage. However, voltage/frequency cannot be blindly scaled in hard real-time systems because DVFS techniques impact on the execution time, and so potentially on the worst-case execution time (WCET) of tasks. This paper presents a new DVFS technique for hard real-time systems that measures dynamically the intra-task slack existing between the actual execution time of a task and its WCET estimation, and exploits it to perform DVFS guaranteeing that the WCET is not affected. Concretely, our approach exploits the slack available due to contention in the use of shared resources in a multi-core system.

Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times

This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot and, thus, adjust its voltage and frequency in order to save energy, while meeting soft timing constraints. This is, in turn, achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15% /spl sim/ 60% CPU energy saving was achieved at the cost of 5%-20% performance penalty.