Dynamic Voltage And Frequency Scaling Techniques Research Articles

Energy Harvesting Deadline Monotonic Approach for Real-time Energy Autonomous Systems

This paper presents an innovative scheduling algorithm designed specifically for real-time energy harvesting systems, with a primary focus on minimizing energy consumption and extending the battery's lifespan. The algorithm employs a fixed priority assignment which is the deadline monotonic policy, we have chosen it for its optimality and superior performance compared to other fixed priority scheduling methods. To achieve a balance between energy efficiency and system performance, we incorporated a DVFS (Dynamic Voltage and Frequency Scaling) technique into the algorithm. This adaptive approach enables precise control over the processor's operating frequency, effectively managing energy consumption while ensuring satisfactory system functionality. The core objective of our scheduling algorithm centers on optimizing energy utilization in real-time energy harvesting systems, specifically tailored to extend the battery's operational life. Rigorous evaluations, including comprehensive comparisons against established fixed priority scheduling algorithms, validate the algorithm's efficacy in significantly reducing energy consumption while preserving the system's overall functionality. By combining the deadline monotonic policy and DVFS technique, our proposed algorithm emerges as a promising solution for energy-autonomous systems, contributing to the advancement of sustainable energy practices in real-time applications. As energy harvesting technologies continue to progress, our algorithm holds valuable potential to provide critical insights for enhancing the efficiency and reliability of future energy harvesting systems.

A 33nW Fully Autonomous SoC With Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for mm-Scale System-in-Fiber.

This article presents a fully autonomous system-on-chip (SoC) that can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other in-fiber SoCs for ultra-low-power (ULP) sensing applications. Utilizing a custom switched capacitor energy harvesting and power management unit (EHPMU), the SoC can efficiently redistribute and reuse harvested energy along the fiber. Integrated on-chip, the ULP RISC-V digital core and temperature sensor enable energy-efficient sensing and computation at nanowatt power levels. A dedicated ripple boot-up and cooperative dynamic voltage and frequency scaling (DVFS) further optimize the operation and physical size of the system. Fabricated in 65 nm, measurement results show that the proposed SoC achieves 33 nW power consumption for the whole chip under 92 Lux lighting condition and can reduce control power down to 2.7 nW for the EHPMU. With the proposed power sharing and cooperative DVFS techniques, the SoC reduces the illuminance needed to stay alive by >7× down to 12 Lux. Integrated into a mm-scale polymer fiber, our SoC demonstrates the feasibility of fully autonomous and ULP on-body sensing systems in resource-constrained fiber environments.

Dynamic Voltage and Frequency Scaling and Duty-Cycling for Ultra Low-Power Wireless Sensor Nodes

Energy efficiency presents a significant challenge to the reliability of Internet of Things (IoT) services. Wireless Sensor Networks (WSNs) present as an elementary technology of IoT, which has limited resources. Appropriate energy management techniques can perform increasing energy efficiency under variable workload conditions. Therefore, this paper aims to experimentally implement a hybrid energy management solution, combining Dynamic Voltage and Frequency Scaling (DVFS) and Duty-Cycling. The DVFS technique is implemented as an effective power management scheme to optimize the operating conditions during data processing. Moreover, the duty-cycling method is applied to reduce the energy consumption of the transceiver. Hardware optimization is performed by selecting the low-power microcontroller, MSP430, using experimental estimation and characterization. Another contribution is evaluating the energy-saving design by defining the normalized power as a metric to measure the consumed power of the proposed model per throughput. Extensive simulations and real-world implementations indicate that normalized power can be significantly reduced while sustaining performance levels in high-data IoT use cases.

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With the advent of mobile processors integrating CPU and GPU, high-performance tasks, such as deep learning, gaming, and image processing are running on mobile devices. To fully exploit CPU and GPU's capability on mobile devices, we need to utilize their processing capability as much as possible. However, it is challenging due to the nature of mobile devices whose users are sensitive to battery consumption and device temperature. Many researchers have studied techniques enabling energy-efficient operations in mobile processors, mostly at managing the temperature and power consumption below predefined thresholds. DVFS (Dynamic Voltage and Frequency Scaling) is a technique that reduces heat generation and power consumption from the circuit by adjusting CPU or GPU voltage-frequency levels at runtime. To best utilize its benefits, many DVFS techniques have been developed for mobile processors. Still, it is challenging to implement a DVFS that performs ideally for mobile devices, and there are several reasons behind this difficulty.

Analytical Energy Model Parametrized by Workload, Clock Frequency and Number of Active Cores for Share-Memory High-Performance Computing Applications

Energy consumption is crucial in high-performance computing (HPC), especially to enable the next exascale generation. Hence, modern systems implement various hardware and software features for power management. Nonetheless, due to numerous different implementations, we can always push the limits of software to achieve the most efficient use of our hardware. To be energy efficient, the software relies on dynamic voltage and frequency scaling (DVFS), as well as dynamic power management (DPM). Yet, none have privileged information on the hardware architecture and application behavior, which may lead to energy-inefficient software operation. This study proposes analytical modeling for architecture and application behavior that can be used to estimate energy-optimal software configurations and provide knowledgeable hints to improve DVFS and DPM techniques for single-node HPC applications. Additionally, model parameters, such as the level of parallelism and dynamic power, provide insights into how the modeled application consumes energy, which can be helpful for energy-efficient software development and operation. This novel analytical model takes the number of active cores, the operating frequencies, and the input size as inputs to provide energy consumption estimation. We present the modeling of 13 parallel applications employed to determine energy-optimal configurations for several different input sizes. The results show that up to 70% of energy could be saved in the best scenario compared to the default Linux choice and 14% on average. We also compare the proposed model with standard machine-learning modeling concerning training overhead and accuracy. The results show that our approach generates about 10 times less energy overhead for the same level of accuracy.

DV-DVFS: merging data variety and DVFS technique to manage the energy consumption of big data processing

Data variety is one of the most important features of Big Data. Data variety is the result of aggregating data from multiple sources and uneven distribution of data. This feature of Big Data causes high variation in the consumption of processing resources such as CPU consumption. This issue has been overlooked in previous works. To overcome the mentioned problem, in the present work, we used Dynamic Voltage and Frequency Scaling (DVFS) to reduce the energy consumption of computation. To this goal, we consider two types of deadlines as our constraint. Before applying the DVFS technique to computer nodes, we estimate the processing time and the frequency needed to meet the deadline. In the evaluation phase, we have used a set of data sets and applications. The experimental results show that our proposed approach surpasses the other scenarios in processing real datasets. Based on the experimental results in this paper, DV-DVFS can achieve up to 15% improvement in energy consumption.

Autonomous Power Management With Double-QReinforcement Learning Method

Energy efficiency and autonomous power management are extremely important for mobile-edge computing. Reducing energy consumption of a number of applications running concurrently in mobile devices while maintaining performance poses a challenge to energy optimization due to the limited capacity of the embedded battery. To extend battery life and offer a long-lasting working energy, dynamic voltage and frequency scaling (DVFS) has been widely used in mobile devices for energy consumption minimization. However, most conventional DVFS techniques scale operating frequency based on static policies, and thus, they are difficult to be adapted to systems of varied conditions. In order to improve adaptivity, in this article, we proposed a Double- Q power management approach to scale operating frequency based on learning. The Double- Q method stores two Q tables and two corresponding update functions. In each decision point, either of Q tables is randomly chosen and updated, while the other is used for the measurement. This mechanism reduces the overestimation in Q values, consequently enhancing the accurateness of frequency predictions. To evaluate the effectiveness of our proposed approach, a Double- Q governor is implemented in the Linux kernel. Our approach is computationally light, and experimental results indicate that it achieves at least 5– $18\%$ total energy saving compared to ondemand and conservative governors, as well as Q learning-based method.

Thermal Aware Task Scheduling for Enhanced Cyber-Physical Systems Sustainability

Cyber-Physical Systems (CPS) are increasingly used in a variety of transportation, healthcare, electricity grid, and other applications. Thermal stress is often a major concern for processors embedded in such systems. High operating temperatures can dramatically shorten processor life. This, in turn, can require provisioning of significant amounts of additional computational hardware to withstand more frequent failures, with obvious implications for sustainability. This paper describes a novel approach to reduce thermally-induced damage in CPS processors by targeting Dynamic Voltage and Frequency Scaling (DVFS) to high-activity task phases. That is, by preferentially slowing down high-activity task phases, significant additional savings in energy and thermal stress can be attained for a given amount of computational slowdown; this approach is shown to be superior to conventional methods that use DVFS without regard to activity levels. Also, our proposed task reassignment across cores is driven by estimates of current core reliability, which is superior to the usual approach of simply using either current temperature or temperature history. Our approach leads to a significant reliability improvement (around 20 percent) over baseline DVFS techniques.

Implementation of DVFS Technique for Processor Power and Temperature Reduction

In the world, 70−80% of the people directly or indirectly depend on battery operated devices like mobile phone, Electronic tablets, laptops etc. We expect these systems to run at high frequency to complete the tasks as quickly as possible because of this high frequency, system consumes high power this leads to quick battery drain out and increases in systems temperature. So, we are using dynamic voltage and frequency scaling (DVFS) to achieve goal of temperature reduction and energy saving. The Xilinx simulation environment confirms the theory.

Energy-Efficient Intra-task DVFS Scheduling Using Linear Programming Formulation

In real-time embedded systems, minimizing energy consumption is one of the most important tasks. Intra-task dynamic voltage and frequency scaling (DVFS) has been the subject of much research in the task boundary of time-constrained applications for energy reduction. The problem of optimizing energy consumption with respect to intra-task DVFS scheduling can be addressed by assigning proper operational frequencies to individual basic blocks in a program while guaranteeing the deadline. Based on the profile information of a task, we first formulate the problem in terms of integer linear programming (ILP) regarding different assumptions of transition overhead. To verify the effectiveness of ILP formulations, the most representative intra-task DVFS techniques are taken for comparisons. The results of the experiments demonstrate that the proposed ILP method achieves greater energy savings than the existing approaches. Moreover, it determines the optimal scheduling strategy in reasonable execution time for applications with a limited number of blocks.

Energy-Efficient Scheduling for Real-Time Systems Based on Deep Q-Learning Model

Energy saving is a critical and challenging issue for real-time systems in embedded devices because of their limited energy supply. To reduce the energy consumption, a hybrid dynamic voltage and frequency scaling (DVFS) scheduling based on Q-learning (QL-HDS) was proposed by combining energy-efficient DVFS techniques. However, QL-HDS discretizes the system state parameters with a certain step size, resulting in a poor distinction of the system states. More importantly, it is difficult for QL-HDS to learn a system for various task sets with a Q-table and limited training sets. In this paper, an energy-efficient scheduling scheme based on deep Q-learning model is proposed for periodic tasks in real-time systems (DQL-EES). Specially, a deep Q-learning model is designed by combining a stacked auto-encoder and a Q-learning model. In the deep Q-learning model, the stacked auto-encoder is used to replace the Q-function for learning the Q-value of each DVFS technology for any system state. Furthermore, a training strategy is devised to learn the parameters of the deep Q-learning model based on the experience replay scheme. Finally, the performance of the proposed scheme is evaluated by comparison with QL-HDS on different simulation task sets. Results demonstrated that the proposed algorithm can save average <inline-formula><tex-math notation="LaTeX">$4.2\%$</tex-math></inline-formula> energy than QL-HDS.

PL-DVFS: combining Power-aware List-based scheduling algorithm with DVFS technique for real-time tasks in Cloud Computing

In recent years, energy efficiency has emerged as one of the most important design requirements for modern computing systems, ranging from single servers to data centers and Clouds, as they continue to consume an enormous amount of electrical power. Cloud computing can be used to achieve energy efficiency through efficient task scheduling in the distributed environment. This efficient task scheduling helps to improve resource utilization, which, in turn, helps to minimize energy consumption. In this paper, we work toward minimizing energy of directed acyclic graph-structured applications on heterogeneous cloud system. The paper also combines power-aware list-based scheduling algorithm with dynamic voltage and frequency scaling (DVFS) technique for real-time tasks (PL-DVFS) to maintain the quality of service while considering tasks deadlines. The goal of the approach is to improve performance and overall reduced energy consumption comprising CPU energy (busy and idle) and communication energy. Experiments conducted with synthetic workflow graphs clearly demonstrate the advantage of the proposed approach.

Temperature-aware dynamic voltage and frequency scaling enabled MPSoC modeling using Stochastic Activity Networks

The CMOS technology scaling brings new challenges in temperature, reliability, performance and leakage power. Most of the thermal management techniques compromise performance to control thermal behavior of the system by slowing down or turning off processors. In this paper, we use Stochastic Activity Networks (SANs) to model and evaluate the power consumption of a multi-core system with respect to thermal constraints. The Dynamic Voltage and Frequency Scaling (DVFS) technique is used, in our proposed model, for dynamically controlling the temperature of cores. We define multiple thresholds for the temperature of cores and apply the DVFS technique, by assigning lower voltage/frequency to the core with higher temperature. Results obtained from analytically solving the proposed SAN model are compared with the data gathered from experiments on a quad-core system. The accuracy of the proposed model in evaluating power consumption of six CPU-intensive applications is higher than 90% when compared with the experimental data.

Energy-Efficient Scheduling Algorithms for Real-Time Parallel Applications on Heterogeneous Distributed Embedded Systems

Energy consumption minimization is one of the primary design requirements for heterogeneous distributed systems. State-of-the-art algorithms are used to study the problem of minimizing the energy consumption of a real-time parallel application with precedence constrained tasks on a heterogeneous distributed system by introducing the concept of latest finish time (LFT) to reclaim the slack time based on the dynamic voltage and frequency scaling (DVFS) energy-efficient design optimization technique. However, the use of DVFS technique alone is insufficient, and the energy consumption reduction is limited because scaling down the frequency is restricted in practice. Furthermore, these studies merely minimize energy consumption through a local energy-efficient scheduling algorithm, such as reducing the energy consumption for each task on the fixed processor, rather than a global energy-efficient scheduling algorithm, such as reducing the energy consumption for each task on different processors. This study solves the problem of minimizing the energy consumption of a real-time parallel application on heterogeneous distributed systems by using the combined non-DVFS and global DVFS-enabled energy-efficient scheduling algorithms. The non-DVFS energy-efficient scheduling (NDES) algorithm is solved by introducing the concept of deadline slacks to reduce the energy consumption while satisfying the deadline constraint. The global DVFS-enabled energy-efficient scheduling (GDES) algorithm is presented by moving the tasks to the processor slacks that generate minimum dynamic energy consumptions. Results of the experiments show that the combined NDES&GDES algorithm can save up to 36.25-55.65 percent of energy compared with state-of-the-art counterparts under different scales, parallelism, and heterogeneity degrees of parallel applications.

Task aware hybrid DVFS for multi-core real-time systems using machine learning

There have been renewed interest in embedded battery powered devices due to their widespread applications in sectors such as automotive, industrial, and health care. In order to reduce energy consumption and enhance battery life, dynamic voltage and frequency scaling (DVFS) techniques have been applied to processors (one of the most energy consuming components). In order to keep pace with advancements in fabrication technologies, it is important to scale voltage and frequency intelligently; otherwise, DVFS techniques could result in a higher energy consumption. In our previous work, depending on the execution characteristics of real-time tasks, DVFS decisions were made using machine learning method in unicore processors. We also used learning-based approach to select the best real-time DVFS technique for the situation from a set of techniques and proposed a framework that integrates the selection of various scheduling policies and the optimization of existing real-time DVFS techniques in multi-core processors. In this paper, we describe the design of the framework to make an effective learning-based DVFS system, and demonstrate the utility of the generalized learning-based framework using experiments on multi-core real-time systems for both synthetic tasks and benchmark tasks from real applications. Our findings show that the framework is computationally lightweight and effective in reducing energy consumption.

Hybrid DVFS Scheduling for Real-Time Systems Based on Reinforcement Learning

Power consumption is one of the most challenging issues in the design of modern computing systems. In any computational device, processor consumes significant amount of power compared with other components. In order to reduce power consumption, dynamic voltage and frequency scaling (DVFS) has been commonly used in modern processors. In recent years, there has been much research on real-time DVFS techniques. These techniques work with different strategies and perform well under different conditions. However, a single algorithm is not always optimal under different workloads, dynamic slacks, and power settings. Furthermore, the variation in device configuration also affects the suitability of a given DVFS algorithm. Aiming for adaptability, in this paper, we propose a novel reinforcement learning-based approach, which takes a set of existing techniques, specialized to handle different conditions, and switches to the most suitable one in various situations. Experimental results show that the proposed hybrid approach saves more energy than any single policy executing individually.

An adaptive deadline constrained energy‐efficient scheduling heuristic for workflows in clouds

SummaryThere is an increasing interest for cloud services to be provided in a more energy‐efficient way. The growing deployment of large‐scale, complex workflow applications onto cloud computing hosts are facing with crucial challenges in reducing the energy consumption without violating certain quality of service. Dynamic voltage and frequency scaling (DVFS) is a power management technique commonly used to lower the processor frequency and decrease the energy consumption in modern computing systems. However, as lowering processor frequency may result in increased idle time on processors, which may in turn lead to increased overall energy consumption, scaling the processor frequency as low as possible may not always be energy‐efficient. In this paper, we consider cloud hosts with the DVFS technique and focus on the problem of scaling frequency to reduce overall energy consumption of a workflow given an allocation of tasks to hosts and a deadline to complete the execution. We propose a novel scheduling heuristic, which takes the system and application characteristics and the overall energy consumption into account when making frequency scaling decision. The proposed heuristic is evaluated using simulation with four different real‐world applications. The observed results indicate that our heuristic can achieve significant energy saving and outperform the existing approaches. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Performance of Clock Mesh Under Dynamic Voltage and Frequency Scaling

Mesh based clock distribution is gaining popularity in microprocessor based designs, because of its tolerance to skew induced by process variations in Deep Sub-Micron technologies (DSM). In the recent past, there has been much research on reduction of power consumed by any chip and Dynamic Voltage and Frequency Scaling (DVFS) has emerged as one of the prominent methods for reducing the power. In this work, we first synthesize a capacitance driven clock mesh and study the variations of skew when the mesh is operated under a DVFS technique. Based on the observations, a novel method to reduce the skew variations is then proposed.

Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Embedded GPUs

Dynamic voltage and frequency scaling (DVFS) is a key technique for reducing processor power consumption in mobile devices. In recent years, mobile system-on-chips (SoCs) has supported DVFS for embedded graphics processing units (GPUs) as the processing power of embedded GPUs has been increasing steadlily. The major challenge of applying DVFS to a processing unit is to meet the quality of service (QoS) requirement while achieving a reasonable power reduction. In the case of GPUs, the QoS requirement can be specified as the frame-per-second (FPS) which the target GPU should achieve. The proposed DVFS technique ensures a consistent GPU performance by scaling the operating clock frequency in a way that it maintains a uniform FPS.

PMaC's green queue: a framework for selecting energy optimal DVFS configurations in large scale MPI applications

SummaryThis article presents Green Queue, a production quality tracing and analysis framework for implementing application aware dynamic voltage and frequency scaling (DVFS) for message passing interface applications in high performance computing. Green Queue makes use of both intertask and intratask DVFS techniques. The intertask technique targets applications where the workload is imbalanced by reducing CPU clock frequency and therefore power draw for ranks with lighter workloads. The intratask technique targets balanced workloads where all tasks are synchronously running the same code. The strategy identifies program phases and selects the energy‐optimal frequency for each by predicting power and measuring the performance responses of each phase to frequency changes. The success of these techniques is evaluated on 1024 cores on Gordon, a supercomputer at the San Diego Supercomputer Center built using Intel Xeon E5‐2670 (Sandybridge) processors. Green Queue achieves up to 21% and 32% energy savings for the intratask and intertask DVFS strategies, respectively. Copyright © 2013 John Wiley &amp; Sons, Ltd.