Dynamic Threshold MOS Research Articles

16-nW 0.5-V low-pass filter for bio-signal applications

A low-voltage, ultra-low power fully differential low-pass filter for bio-signal applications using multiple-input fully differential operational transconductance amplifiers (OTA) is presented in this article. The multiple inputs of OTA can be achieved using multiple-input dynamic threshold MOS transistor (MIDT-MOST) technique. The novelty of this work is to exhibit the proposed filter using multiple-input OTAs, which leads to a reduction in the number of active OTAs and power consumption. The fourth-order low-pass filter that is cascaded by two second-order filters has been presented. The fourth-order low-pass filter is designed and simulated in the Cadence environment using the 0.18 μm CMOS technology from TSMC at a supply voltage of 0.5 V. The simulation results show that the filter consumes 16 nW of power at a bandwidth of 110 Hz, has a total harmonic distortion (THD) of 1 % at 204.96 mV input amplitude, and provides dynamic range of 69.24 dB. These results indicate that the proposed low-pass filter can be applied to bio-signal processing applications.

A 40 mV cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting

In this paper, a cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting is proposed. The relationship between enhancing the clock swing amplitude and lowering the input voltage for a cross-coupled charge pump (CCCP) is analyzed. Based on the existing one-shot start-up mechanism, a series-parallel bootstrap clock booster (SP-BCB) for boosting the clock amplitude is proposed to lower the cold start voltage. Besides, a dynamic threshold MOS (DTMOS) technique for dynamically changing the threshold voltage of MOS transistors is used to achieve better conduction and leakage current suppression. The complete circuit is simulated in a 0.18-μm CMOS process. The simulated results demonstrate that using DTMOS technique and enhancing the clock swing amplitude can contribute to lowering the input voltage. The SP-BCB-based CCCP can boost the input voltage from 40 mV to 668 mV for a 500 MΩ load in 100 m s, which meets the requirement for one-shot start-up mechanism, realizing 40-mV integrated cold start for thermoelectric energy harvesting (TEH).

A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

UTBB FD-SOI MOSFET with SELBOX in DTMOS Configuration

Abstract— For the first time, Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) n-channel with Dynamic Threshold MOS configuration (DTMOS) using the SELBOX (Selective Buried OXide) substrate will be analyzed. The drain and substrate current, transconductance (gm) and Subthreshold Slope (SS) will be compared in the DTMOS mode and the standard biasing configuration for different gap width (WGAP) of SELBOX. Additionally, the output conductance and the transconductance gain also studied through numerical simulations. The results indicate that the SELBOX structure in DTMOS mode is competitive candidates for analog applications.

A 0.6-V 11-uW PVT tolerant DTMOS inverter based OTA

This paper presents the design of a process-voltage-temperature (PVT) variation tolerant inverter-based operational transconductance amplifier (OTA) employing both a dynamic threshold MOS (DTMOS) technique and a constant voltage biasing (CVB) scheme. The proposed inverter-based OTA offers a higher bandwidth due to implemented DTMOS technique, which realizes higher input transconductance value than a conventional inverter-based OTA design. Simulation results show that the proposed OTA achieves superior slow-slow (SS) corner performance under PVT variations than the conventional inverter-based OTA while consuming only 11-uW and providing a figure of merit (FoM) of 7.0-MHz.pF/uA. As a result, DC gain and unity-gain bandwidth (UGBW) of the proposed OTA improve by 27% and 32% at SS corner under the PVT variations, respectively.

Fully differential fifth-order dual-notch low-pass filter for portable EEG system

This paper presents a new fully differential fifth-order dual-notch low-pass filter based on multiple-input multiple-output operational transconductance amplifiers (MIMO OTA). This work shows that MIMO OTA-based fifth-order dual-notch filter can reduce the number of used OTAs, resulting in simplified realization and low-power consumption. The multiple-input OTA is obtained by using the multiple-input dynamic threshold MOS (DTMOS) technique without additional differential pairs. A simple common-mode feedback technique has been used; thus, fully differential OTA can be easily obtained. The proposed dual-notch low-pass filter can be applied to electroencephalogram (EEG) detection system to reject the 50 Hz powerline interference and the third harmonic 150 Hz. The proposed filter has been simulated using Cadence environment with 0.18 µm TSMC CMOS process. The power supply of 0.5 V is used and the total power consumption of the MIMO OTA is 17.5 nW. The proposed filter provides 49.7 dB dynamic range for 1% total harmonic distortion (THD) for a sine input signal of 250 mVpp at 10 Hz. At 50 Hz and 150 Hz the notch depths of attenuation are respectively −37.2 dB and −47.4 dB. The pre-layout simulation results are in good agreement with the theory.

Low-Voltage and Low-Power Analog Multiplier/Divider Using OTA Based on DTMOS Transistor

A low-voltage and low-power current mode analog multiplier/divider design is presented in this paper. The multiplier/divider is based on operational transconductance amplifier (OTA) utilizing dynamic threshold MOS (DTMOS) structure and consists of only three OTAs. The circuit has the ability of consuming low power and requiring low voltage power supplies. 0.13µm IBM CMOS technology parameters are used to simulate the suggested multiplier/divider design and the simulation results are obtained using LTspice program. The current mode analog multiplier/divider architecture consumes only 12.07nW and requires ±0.2V of supply voltages thanks to employing DTMOS transistor. The simulation results agree well with the expected results.

Design of Low-Voltage and Low-Power DTMOS Based Analog Multiplier Utilizing Current Squarer

ABSTRACT In this paper, a low-voltage and low-power current mode analog multiplier design is presented. The multiplier is based on dynamic threshold MOS (DTMOS) structure. The proposed topology consists of four current squarer circuits and one subtractor structure. Each squarer cell has two MOS transistors and the subtractor consists four MOS transistors. Therefore, the multiplier employs 12 MOS transistors excluding resistors and biasing current sources. The introduced circuit consumes low power and requires low voltage power supplies thanks to DTMOS structure. The current mode analog multiplier architecture has a power consumption of 99.76nW and involves a single supply voltage of 0.3 V owing to including DTMOS transistor. The analysis results agree well with the expected results. The behaviour of the suggested multiplier has been verified through the analysis results with the help of LTspice simulation software and 0.13 µm IBM CMOS technology parameters have been used for simulation.

Design of low-voltage and low-power current-mode DTMOS transistor based full-wave/half-wave rectifier

A low-voltage and low-power current mode rectifier based on dynamic threshold MOS (DTMOS) transistor is proposed in this paper. The suggested one input–two output rectifier architecture provides full-wave rectification and half-wave rectification. Full-wave rectifier consists of only 6 MOS transistors (excluding 1 MOS transistor in half-wave rectifier part) and is designed without the necessity of using active and passive circuit elements. The proposed rectifier design is simulated using 0.13 µm IBM CMOS technology parameters. The full-wave rectifier circuit requires ± 0.25 V of supply voltages and consumes only 4.36 nW thanks to employing DTMOS transistor structure.

DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier

Analog multiplication circuits are very important block structures which are widely used in analog signal applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to supply voltage. In this study, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors and low power consumption and high bandwidth have been obtained. In improver, the bandwidth was obtained at values of 3.63 GHz, temperature variation, total harmonic distortion and intermodulation products of the proposed multiplier were examined. Monte Carlo analysis was performed and error analysis of the dimensioning of the circuit was examined. In summation to the high bandwidth, a low power consumption of 44.5 µW has been achieved and the supply voltage of 0.2 V has been achieved to operate in full-scale input range.

Effect Of Body Biasing On 0.13 Um CMOS Transistor

Complementary metal-oxide semiconductor (CMOS) consist of n-type metal-oxide semiconductor field effect transistor (NMOS) and p-type MOSFET (PMOS). In common practice, only three terminals of these transistors are used, namely gate, source and drain. Meanwhile, the fourth terminal, which is body terminal is tied to source. Changing body terminal bias causes the transistor to have a body effect. In this work, optimum body biasing for 0.13 μm NMOS and PMOS are identified. Effect of body biasing to the MOSFETs are investigated. In addition, how body biases affect CMOS circuits are also observed. Three type of body biasing are considered, namely Forward Body Biasing (FBB), Reverse Body Biasing (RBB), and Dynamic Threshold MOS (DTMOS). Drain current, Id versus gate voltage, VG and drain current, Id versus drain-source voltage, VDS for FBB, RBB and DTMOS are simulated to determine the optimum operating point for each biasing technique. To observe the effect of body biasing techniques on the circuits, inverter and common source amplifier are constructed using FBB, RBB and DTMOS. In addition, the circuits also constructed in zero body biasing (ZBB) for comparison. The results show that, optimum body biasing is at 0.6 V for all three body biasing techniques. FBB and DTMOS cause the threshold voltage, Vth to decrease but increase the leakage current. On the other hand, RBB causes increase in threshold voltage, Vth yet reduces the leakage current of the CMOS. The results obtained in this work will enable other circuit designers to determine the optimum FBB, RBB and DTMOS operating point.

Ultra-low voltage and low-power voltage-mode DTMOS-based four-quadrant analog multiplier

This paper presents a new four-quadrant analog multiplier based on a dynamic threshold MOS (DTMOS). The attractive features of this DTMOS transistor-based multiplier are its supply voltages and total power consumption, which were determined as ± 0.2 V and 18.4 nW, respectively. In addition, the study found no influences of the bulk effect of the transistors used in the proposed multiplier circuit. The layout of the four-quadrant analog multiplier occupied an active area of 44.6 µm × 21.93 µm and was drawn using Cadence Environment software, while the post-layout simulation results were performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. All theoretical results and post-layout simulations confirmed the performance of the proposed circuit.

Deep-Cryogenic Voltage References in 40-nm CMOS

The increasing interest in electronics specifically designed to control quantum processors is currently driven by the quest for large-scale quantum computing. A promising approach is emerging based on the use of CMOS devices operating at deep-cryogenic temperatures, and several essential components have been demonstrated to operate at such temperatures, from basic MOSFETs to field-programmable gate arrays. In this letter, we show, for the first time, a voltage reference in a standard CMOS technology that can guarantee a stable voltage over a wide range of temperatures from 300 K down to deep-cryogenic temperatures. By exploiting CMOS transistors in dynamic-threshold MOS configuration, the proposed reference occupies only 445 $\mu \text{m}^{2}$ in a standard 40-nm CMOS process, while showing a temperature coefficient below 0.8 mV/K over the temperature range from 4 to 300 K. These results demonstrate the feasibility of wide-range cryogenic voltage references to enable future cryogenic applications.

Ultra-Low voltage-power DTMOS based full-wave rectifier

In this paper, dynamic threshold MOS (DTMOS) transistor based full-wave rectifier with ultra-low power consumption is presented. The proposed circuit composed of only four NMOS and seven DTMOS transistors when many rectifier circuits consist of passive circuit components such as diodes, resistors and active circuit elements. The layout occupies an active area of 24.6 µm × 65.01 µm and post-layout simulation results performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. The rectifier circuit with ±0.2 V DC supply voltages can be operated up to approximately 500 MHz and consumes only 2.83 nW thanks to the DTMOS transistors.

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16- $\mu \text{m}$ CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.

Design techniques for low-voltage analog integrated circuits

Abstract In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

DTMOS-Based Pulse Transformer Boost Converter With Complementary Charge Pump for Multisource Energy Harvesting

An energy-harvesting system that accommodates both discrete-time or continuous-time energy sources simultaneously is presented. The core dc–dc converter is a pulse transformer boost converter using dynamic threshold MOS transistor that self-starts at 36 mV-input voltage and generates bipolar output voltages up to ±2.5 V. Employing the dynamic body bias technique to the boost converter power transistor improves power efficiency at sub-300-mV input voltages up to two times over the identical transistor in a conventional configuration. At large harvested power, the source-to-body diode of the power transistor functions as an input voltage limiter. Dynamic threshold MOSFET (DTMOS) also increases transistor saturation current and output power compared to conventional transistors at similar input voltage. Instead of using a linear shunt regulator, excess power is dissipated by internal loss of a bipolar-clocked cross-coupled charge pump. An on-chip voltage-controlled oscillator, which generates clock frequency in proportion to the harvested power, and a unipolar-to-bipolar level shifter are included to drive the charge pump designed. The circuit prototypes are fabricated by using the UMC 0.13- $\mu\mbox{m}$ CMOS process with the triple-well option.

DTMOS Transistor with Self-Cascode Subcircuit for Achieving High Bandwidth in Analog Applications

work, an improved dynamic threshold MOS (DTMOS) transistor with self-cascode subcircuit has been proposed in this work. By adopting the self-cascode subcircuit, the proposed DTMOS transistor could be operated at supply voltage over 0.7V. Apart from this, simulation results for the proposed DTMOS, also demonstrate improvement in the transconductance and bandwidth by a factor of 2.31 and 1.59 respectively. Furthermore, the current driving capability of proposed DTMOS transistor has increased by a factor of 1.87. To validate the proposed concept and its applications in analog circuits, a current mirror and a differential amplifier have been designed in 180nm CMOS technology. Both circuits are able to operate at higher bandwidth as compared to their conventional counterparts. The Monte Carlo simulations reflect the robustness of the circuits to device mismatch errors. The proposed DTMOS transistor is more suitable for large signal circuits such as mixer and voltage control oscillator. Keywordsthreshold MOS transistor (DTMOS), Self-Cascode, bandwidth, transconductance, analog integrated circuits.

Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

UTBB FDSOI (Ultrathin-Body-and-Buried-Oxide Fully-Depleted-SOI) devices have been studied for the 14nm and 10nm technology nodes, thanks to reduced SCEs, better threshold voltage (VT) control, better reliability, better power efficiency at high frequency operation, higher compatibility with existing CMOS technology (1). In PDSOI a technique has been proposed to further improve some digital and analog parameter, called dynamic threshold (DT) MOS mode, where the front gate (VGF) is connected to the body. During the VGF sweep, the body bias is also increased, which dynamically reduces the VT. (2) In UTBB FDSOI devices, this concept has been applied in 3 operation modes: the simple DT (VGB = VGF) (3,4), the enhanced DT (VGB = kVGF) (3,4) and the inverse DT (VGF = kVGB) (4). In this case, the VGF is tied to the VGB, instead of the body and the VT is decreased when VGB increases. (3,4). Figure 1 schematically shows a DT-UTBB SOI structure. The device that was used in this work was fabricated in imec, Belgium. The SOI wafer has a nominal value for silicon film thickness (tSi) of 20 nm and buried oxide thickness (toxb) of 10 nm. The front oxide thickness (toxf) is 5 nm. The gate material is TiN. The dimensions of the device are channel length (L) of 105 nm and the channel width of 920 nm. A p-type ground plane (GP) implantation was done which is considered as a back gate. More process information can be found in (5). The goal of this work is to determine the VT of DT UTBB SOI transistors using a simple analytical model proposed by Martino et al (6), with quantum confinement effect (7,8). The equations [1], [2] and [3] were used to determine the value of VT and the equations [4], [5] and [6] represent the variation of tSi and toxf due to the quantum confinement effect. In the analytical model, the GP concentration was set to 1018cm-3 and the metal work function at 4.62 V (TiN). By the VT x VGB curve calculated from the analytical model, it is possible to determine the value of VT of the UTBB operating in: DT, eDT and inverse-eDT modes. In figure 2 the straight line represents the analytical model VT as a function of VGB, and the dashed lines are related to the following conditions: VGB = VGF, VGB = kVGF and VGF = kVGB, for k = 2. These curves represent the three operation modes of DT: simple DT, enhanced DT and inverse eDT mode respectively. The intersection points between the dashed and the straight lines represent the extraction point of VT of a device in DT, eDT and inverse eDT mode, respectively. For DT and eDT modes the VT of DT UTBB SOI is the value of VT of intersection point (Y-axis). In case of inverse eDT the VT is represent by the value of VGB of the intersection (X-axis). The same analysis was done for different values of k. The value of VT obtained from figure 2 was compared with experimental data in figure 3 and a good agreement was observed. In figure 3, for k=0 the operation mode of the transistor is the conventional mode, where VGB = 0V. This method of extraction of the threshold voltage in DT UTBB devices is simple and effective. (1) B.-Y. Nguyen et al., Advanced Substrate News (2014). (2) J.P. Colinge, IEEE Trans. Electron Devices, 44, 845 (1987). (3) V. Kilchytska et al., Solid State Electronics, 84, 28-37 (2013). (4) K.R.A. Sasaki et al., Proceedings of the IX ICCDCS Conference, 57 (2014). (5) N. Collaert et al., Proceedings of IEEE International SOI Conference, 1 (2009). (6) J.A. Martino et al., Electron Letters, 26, 1462-1464 (1990). (7) S. Burignat et al., Solid-State Electronics, 54, 213-219 (2010). Figure 1

Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

FinFET technology is prone to suffer from line edge roughness (LER)-based V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variation with scaling. It also lacks a simple implementation of multiple V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> than FinFET due to single gate control. However, it is capable of multiple V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , which leads to circuit level power optimization.