Dynamic Reconfiguration Techniques Research Articles

Dynamic partial reconfiguration scheme for fault‐tolerant FFT processor based on FPGA

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems

Cache vulnerability due to soft errors is one of the reliability concerns in embedded systems. Dynamic reconfiguration techniques are widely studied for improving cache energy without considering the implications of cache vulnerability. Maintaining a useful data longer in the cache can be beneficial for energy improvement due to reduction in miss rates, however, longer data retention negatively impacts the vulnerability due to soft errors. This paper studies the tradeoff between energy efficiency improvement and reduction in cache vulnerability during cache reconfiguration. We propose a heuristic approach for both intertask and intratask cache reconfiguration in multitasking systems. Experimental results demonstrate that our proposed approach can significantly improve both vulnerability (25% on average) and energy efficiency (21% on average) for data cache without violating real-time constraints.

Simulation and analysis of reconfigurable assembly systems based on R-TNCES

ABSTRACTRecent research indicates that dynamic reconfiguration techniques can be applied to manufacturing systems to reduce energy consumption by switching energy-intensive components in a timely manner between their working and idle modes during system runtime because these components consume less energy in their idle modes than in their working modes. The current work studies reconfigurable assembly systems with such dynamic reconfiguration techniques by abstracting them as reconfigurable discrete event systems, considering only their logic behavior and properties. The formalism, R-TNCES (reconfigurable timed net condition/event systems), a modular extension of the well-known Petri nets, is used as a system modeling and analysis tool. The simulation of system global reconfigurations is guided by command inserting, whereas the simulation of local reconfigurations is automatic because their execution time is computed a priori by a proposed algorithm. Finally, qualitative properties specified by computation tree logic and quantitative analysis regarding energy-efficiency are performed by using the software SESA.

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration technique can be used to enable energy efficiency in a generic IoT node that exploits a Field Programmable Gate Array (FPGA) device. Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices. Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance. More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard. To this aim, a case study of a video filtering system is proposed and analyzed by dynamically loading three different hardware filters from the management software running on a Linux-based device. With more details, the presented analytical framework allows for a direct comparison between the energy efficiency of a dynamic partially reconfigurable device and a static non-reconfigurable one. The estimated timing conditions that allow the dynamic partially reconfigurable process to achieve relevant energy efficiency with respect to the corresponding static architecture are also outlined.

Analysis and Control of Dynamic Reconfiguration Processes of Manufacturing Systems

Dynamic reconfiguration techniques can greatly improve the flexibility and reliability of manufacturing systems. However, different from static reconfigurable systems, system behavior during dynamic reconfiguration processes is quite complex due to possible concurrence of system structure changes and events inside unaltered components. This increases the difficulty in designing and developing dynamic reconfigurable systems. The current paper deals with the analysis and control of dynamic reconfiguration process of manufacturing systems from the perspective of discrete event systems. To this end, the authors improve the reconfigurable timed net condition/event systems formalism by assigning reconfiguration functions with extra permeating time, action ranges, and concurrent decision functions. As a consequence, nondeterministic behavior of a dynamic reconfigurable system during dynamic reconfigurations can be specified, while the system correctness, coherence, and safety during reconfigurations can be guaranteed. A reconfigurable manufacturing plant is used as a running example to illustrate the contribution of this paper.

Area efficient SDR receiver without and with dynamic partial reconfiguration

Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as by-product.

Area efficient SDR receiver without and with dynamic partial reconfiguration

Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as by-product.

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

SummaryThe vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.

FPGA-Based Multiple DDoS Countermeasure Mechanisms System Using Partial Dynamic Reconfiguration

In this paper, we propose a novel FPGA-based high-speed DDoS countermeasure system that can flexibly adapt to DDoS attacks while still maintaining system performance. The system includes a packet decoder module and multiple DDoS countermeasure mechanisms. We apply dynamic partial reconfiguration technique in this system so that the countermeasure mechanisms can be flexibly changed or updated on-the-fly. The proposed system architecture separates DDoS protection modules (which implement DDoS countermeasure techniques) from the packet decoder module. By using this approach, one DDoS protection module can be reconfigured without interfering with other modules. The proposed system is implemented on a NetFPGA 10G board. The synthesis results show that the system can work at up to 116.782 MHz while utilizing up to 39.9% Registers and 49.85% BlockRAM of the Xilinx Virtex xcv5tx240t FPGA device on the NetFPGA 10G board. The system achieves the detection rate of 100% with the false negative rate at 0% and false positive rate closed to 0.16%. The prototype system achieves packet decoding throughput at 9.869 Gbps in half-duplex mode and 19.738 Gbps in full-duplex mode.

Dynamic Multiple-Period Reconfiguration of Real-Time Scheduling Based on Timed DES Supervisory Control

Based on the supervisory control theory (SCT) of timed discrete-event systems (TDES), this study presents a dynamic reconfiguration technique for real-time scheduling of real-time systems running on uni-processors. A new formalism is developed to assign periodic tasks with multiple-periods. By implementing SCT, a real-time system (RTS) is dynamically reconfigured when its initial safe execution sequence set is empty. During the reconfiguration process, based on the multiple-periods, the supervisor proposes different safe execution sequences. Two real-world examples illustrate that the presented approach provides an increased number of safe execution sequences as compared with the earliest-deadline-first (EDF) scheduling algorithm.

A new method of fault tolerance based on partial reconfiguration

When field programmable gate array (FPGA) applied in the space, it is easily subjected to the single event upset (SEU) effect which will cause the system breaking down. This paper introduces the principle of dynamic reconfiguration of FPGA, and puts forward a new design method based on embedded system with traditional fault-tolerant methods being analysed. It combines the triple modular redundancy (TMR) technique and the FPGA dynamic partial reconfiguration technique, to make the system complete self-detecting and self-healing. The design has been validated and analysed through simulation and testing, and the results turns to indicate that the new design method has strong ability of fault tolerance as well as highly credibility compared with traditional TMR technique.

A new method of fault tolerance based on partial reconfiguration

When field programmable gate array FPGA applied in the space, it is easily subjected to the single event upset SEU effect which will cause the system breaking down. This paper introduces the principle of dynamic reconfiguration of FPGA, and puts forward a new design method based on embedded system with traditional fault-tolerant methods being analysed. It combines the triple modular redundancy TMR technique and the FPGA dynamic partial reconfiguration technique, to make the system complete self-detecting and self-healing. The design has been validated and analysed through simulation and testing, and the results turns to indicate that the new design method has strong ability of fault tolerance as well as highly credibility compared with traditional TMR technique.

Enhancing the performance of malleable MPI applications by using performance-aware dynamic reconfiguration

We present Flex-MPI, an MPI extension which supports malleability for MPI programs.We introduce a performance-aware dynamic reconfiguring technique for malleability.We implement a prediction model to estimate the performance of MPI programs.We present a simple API to access Flex-MPI functionalities from MPI applications.We demonstrate Flex-MPI capabilities to enhance performance via malleability. The work in this paper focuses on providing malleability to MPI applications by using a novel performance-aware dynamic reconfiguration technique. This paper describes the design and implementation of Flex-MPI, an MPI library extension which can automatically monitor and predict the performance of applications, balance and redistribute the workload, and reconfigure the application at runtime by changing the number of processes. Unlike existent approaches, our reconfiguring policy is guided by user-defined performance criteria. We focus on iterative SPMD programs, a class of applications with critical mass within the scientific community. Extensive experiments show that Flex-MPI can improve the performance, parallel efficiency, and cost-efficiency of MPI programs with a minimal effort from the programmer.

Positioning of PV panels for reduction in line losses and mismatch losses in PV array

Partial shading decreases the power output of PV arrays due to mismatch losses. These losses are dependent on the shading pattern and the relative positions of shaded modules in the array. Various static and dynamic reconfiguration techniques have earlier been proposed to mitigate these losses. In an earlier proposed static reconfiguration technique, the power generation is enhanced by altering the physical location of the PV panels using a random Sudoku configuration without modifying the TCT (Total-Cross-Tied) based electrical connections. However, this arrangement faces drawbacks due to ineffective dispersion of shade and significant increase in wiring required. In this work, an optimal Sudoku arrangement to overcome these drawbacks is formulated. Further analysis indicate that the global peak of the optimal Sudoku based PV array occurs as the right most peak in the curve for most shading conditions, thus evidently obviating the need for complex MPPT (Maximum-Power-Point-Tracking) algorithms. The proposed configuration is compared with various other existing reconfiguration schemes in terms of power output and the comparison is presented. In addition, a general formulation is proposed to expand this pattern to any generic array. A strategy is also proposed to make such an interconnection practicable for very large size PV arrays.

ReKonf: Dynamically reconfigurable multiCore architecture

The increased transistor count resulting from ever-decreasing feature sizes has enabled the design of architectures containing many small but efficient processing units (cores). At the same time, many new applications have evolved with varying performance requirements. The fixed architecture of multiCore platforms often fails to accommodate the inherent diverse requirements of different applications. We present a dynamically reconfigurable multiCore architecture that detects program phase change at runtime and adapts to the changing program behavior by reconfiguring itself. We introduce simple but efficient performance counters to monitor vital parameters of reconfigurable architectures. We also present static, dynamic and adaptive reconfiguration techniques for reconfiguring the architecture. Our evaluation of the proposed reconfigurable architecture using an adaptive reconfiguration technique shows an improvement of up to 23% for multi-threaded applications and up to 27% for multiprogrammed workloads over that on statically chosen architectures, and up to 41% over the baseline SMP configuration.

A Modeling Tool for Dynamically Reconfigurable Systems

In this paper, we suggest a tool dedicated to model systems that support the dynamic partial reconfiguration. The purpose of this tool is to provide an abstract view of the developed application. It facilitates the task of the designer by abstracting many low level details and design stages. The proposed tool enables the modeling of the application to be implemented by setting its different components and the constraints to be respected namely: reconfigurable modules, static modules, the link between the application modules, the constraints on the distribution of the area of Field-Programmable Gate Arrays (FPGA) etc. The information entered through a graphical interface of the tool will be used to generate the necessary data for Xilinx tools to pursue the various implementation stages of the dynamic partial reconfiguration technique

Dynamic Reconfigurable Component for Cloud Computing Resources

In recent years a new concept of IT organization emerged, the Cloud Computing. With This new concept, the resources are dynamically scalable, virtualized and provided to users as a service on the Internet. It is primarily intended to meet the demands of users and allow them access to virtually unlimited resources. This model motivates many academic institutions and non-academics as well to develop open-source solutions to improve performance. Among these techniques, dynamic reconfiguration of cloud resources has to take an interest. In this paper an approach for optimization resources is presented, based on dynamic reconfiguration techniques. In fact, a Dynamic Reconfigurable Component (DRC) is proposed to be added to the cloud system, that optimize the use of cloud resources and enable dynamic resource allocation. Then, the implementation of this DRC component is provided.

Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input

Distance-Ranked Fault Identification (DRFI)is a dynamic reconfiguration technique which employs runtime inputs to conduct online functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set of functionally identical bitstream configurations are created which utilize alternate hardware resources in the FPGA fabric. An ordering is imposed on the configuration pool as updated by the PageRank indexing precedence. The configurations which utilize permanently damaged resources and hence manifest discrepant outputs, receive lower rank are thus less preferred for instantiation on the FPGA. Results indicate accurate identification of fault-free configurations in a pool of pregenerated bitstreams with a low number of reconfigurations and input evaluations. For MCNC benchmark circuits, the observed reduction in input evaluations is up to 75% when comparing the DRFI technique to unguided evaluation. The DRFI diagnosis method is seen to isolate all 14 healthy configurations from a pool of 100 pregenerated configurations, and thereby offering a 100% isolation accuracy provided the fault-free configurations exist in the design pool. When a complete recovery is not feasible, graceful degradation may be realized which is demonstrated by the PSNR improvement of images processed in a video encoder case study.

A 1 mJ/Frame Unified Media Application Processor With Dynamic Analog-Digital Mode Reconfiguration for Embedded 3D-Media Contents Processing

In this paper, a unified media application processor (UMAP) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP integrates parallel and sequential processing layers which consist of heterogeneous functional IPs for general media contents processing on today's application processors (AP). Based on the heterogeneous many-core platform, UMAP supports not only graphics and vision processing for real-time augmented reality (AR) but also disparity estimation and 3D display synthesis for 3D-view AR acceleration. A new concept of 3D-view AR which synthesizes 3D display contents from two vertically aligned stereo images and a self-constructed disparity map is introduced to achieve true realism for next generation mobile devices. For low-cost 3D-view AR processing, a homography-based disparity estimation (HDE) algorithm is proposed to construct a disparity map between two stereo images with small implementation overhead. For real-time and energy-efficient system organization, workload-balanced 3-stage pipelined architecture and a mixed-mode feature extraction engine (FEE) are also implemented in UMAP. The 3-stage pipelined system which consists of graphics, vision, and display operation stages reduces per-frame execution latency, while dynamic analog/digital mode reconfiguration based on mixed-mode FEE reduces per-frame energy dissipation, so real-time energy-efficient 3D-view AR can be realized in UMAP. FEE performs high-speed corner detection for vision processing based on four pairs of analog current contention logics (CCLs). Especially, a diode-connected current sensing stabilizer (CSS) in each CCL reduces minimum sensing current for corner detection, so average power consumed in CCL is reduced by 44.9%. In 2D or 3D-view AR processing, FEE with four CCLs replaces the parallel processing core cluster which is the most power hungry IP in UMAP, so 96.7% of cluster power and 99.1% of target detection time are saved in real operation. Based on the 3-stage pipelined architecture with the dynamic mode reconfiguration technique, the entire UMAP achieves up to 64.4% of energy reduction compared to the previous state-of-the-art media processors in full operation.

Ursa

Enterprise and cloud data centers are comprised of tens of thousands of servers providing petabytes of storage to a large number of users and applications. At such a scale, these storage systems face two key challenges: (1) hot-spots due to the dynamic popularity of stored objects; and (2) high operational costs due to power and cooling. Existing storage solutions, however, are unsuitable to address these challenges because of the large number of servers and data objects. This article describes the design, implementation, and evaluation of Ursa, a system that scales to a large number of storage nodes and objects, and aims to minimize latency and bandwidth costs during system reconfiguration. Toward this goal, Ursa formulates an optimization problem that selects a subset of objects from hot-spot servers and performs topology-aware migration to minimize reconfiguration costs. As exact optimization is computationally expensive, we devise scalable approximation techniques for node selection and efficient divide-and-conquer computation. We also show that the same dynamic reconfiguration techniques can be leveraged to reduce power costs by dynamically migrating data off under-utilized nodes, and powering up servers neighboring existing hot-spots to reduce reconfiguration costs. Our evaluation shows that Ursa achieves cost-effective load management, is time-responsive in computing placement decisions (e.g., about two minutes for 10K nodes and 10M objects), and provides power savings of 15%--37%.