Dynamic Reconfigurable Systems Research Articles

Non-intrusive contextual dynamic reconfiguration of ambient intelligent IoT systems

Internet of Things is the current evolution of the Internet, which is opening tremendous opportunities for a large number of novel applications that promise to revolutionize and improve the quality of human life. For this reason, much attention has been oriented towards this theme from different perspectives. The problem treated by this paper is the necessity of having a mechanism that enables IoT systems to perform with transparency without stops or breaks regardless of the changes that affect the surrounding context. We propose a contextual dynamic reconfiguration process to be applied on the architectural level of IoT systems; the process relies on autonomic computing MAPE-K loop. The originality of our work is the use of architectural styles to make reusable all the architectural evolutions applied on the system.

Dynamically Reconfigurable Systems: A Systematic Literature Review

Reconfigurable systems have evolved as a more comprehensive and better known area in the last years. Reconfigurability is strictly related to the ability to change: the more flexible a system is, the greater is its reconfigurability. Reconfiguration can provide the systems characteristics as self-adaptation, allowing their resources to be used according to the environment in which they are found and, consequently, extracting a better use of these resources. Unmanned Aerial Vehicles (UAVs), mine hoists, mobile robots, and balloon systems are some applications where self-adaptation and reconfiguration are important. Some reconfigurable systems are able to plan their reconfiguration at runtime, i.e., the system sets its new configuration while running. These systems are called Dynamically Reconfigurable Systems (DRSs). This paper aims to investigate DRSs seeking to answer four specific questions: (i) how the different kinds of DRSs are classified in the literature and what is their definitions; (ii) what are the hardware and software platforms, methodologies and techniques engaged in DRSs; (iii) what are the domains of application of DRSs; and, (iv) which countries lead the number of publications in DRSs. To do that, a systematic literature review was conducted, where, at the end, 85 articles between 1995 and 2017 were completely read.

MH-RLE: A Compression Algorithm for Dynamic Reconfigurable System Configuration Files Based on Run-Length Coding

MH-RLE: A Compression Algorithm for Dynamic Reconfigurable System Configuration Files Based on Run-Length Coding

A dynamic partial reconfigurable system with combined task allocation method to improve the reliability of FPGA

Currently most FPGAs use SRAM-based technology, which are susceptible to faults from external electromagnetic radiation or produced by long-time internal overload operation. The dynamic partial reconfigurable (DPR) system, as an emerging technology, provides a promising way to solve this problem by reallocating the tasks in damaged resource areas to non-faulty regions at runtime. Based on such idea, an infrastructure for coordinately executing specialized hardware tasks on a reconfigurable FPGA is presented to achieve the flexibility for tolerating the occurring faults at runtime. Moreover, a method named MER-3D-Contact that combines the maximum empty rectangles (MER) technique with the adjacency heuristic is proposed to allocate tasks in the dynamical partial reconfiguration system for higher resource utilization, higher task acceptance ratio and lower fragmentation ratio. At last, experiments are carried out to evaluate the performance of the proposed system, results show that the proposed system can make the highest improvement 36% without damaged areas and the highest improvement 58% with damaged resources in terms of task acceptance ratio. Thus, the proposed system is expected a wide application in the field of more reliable FPGAs.

Analysis and Control of Dynamic Reconfiguration Processes of Manufacturing Systems

Dynamic reconfiguration techniques can greatly improve the flexibility and reliability of manufacturing systems. However, different from static reconfigurable systems, system behavior during dynamic reconfiguration processes is quite complex due to possible concurrence of system structure changes and events inside unaltered components. This increases the difficulty in designing and developing dynamic reconfigurable systems. The current paper deals with the analysis and control of dynamic reconfiguration process of manufacturing systems from the perspective of discrete event systems. To this end, the authors improve the reconfigurable timed net condition/event systems formalism by assigning reconfiguration functions with extra permeating time, action ranges, and concurrent decision functions. As a consequence, nondeterministic behavior of a dynamic reconfigurable system during dynamic reconfigurations can be specified, while the system correctness, coherence, and safety during reconfigurations can be guaranteed. A reconfigurable manufacturing plant is used as a running example to illustrate the contribution of this paper.

An approach for managing the dynamic reconfiguration of software architectures

Currently, most software systems have a dynamic nature and need to evolve at runtime. The dynamic reconfiguration of software systems is a mechanism that must be dealt with to enable the creation and destruction of component instances and their links. To reconfigure a software system, it must be stopped, patched and restarted; this causes unavailability periods which are always a problem for highly available systems. In order to address these problems, this paper presents an approach called software architecture reconfiguration approach (SAREA). We define for this approach a set of intelligent agents, each of them has a precise role in the functioning and the control of software. Our approach implements a restoring mechanism of software architecture to a fully functional state after the failure of one or more reconfiguration operations; it also proposes a reconfiguration mechanism which describes the execution process of reconfigurations.

Dynamic Partial Reconfiguration of Concurrent Control Systems Specified by Petri Nets and Implemented in Xilinx FPGA Devices

This paper proposes a novel design concept of concurrent control systems specified by interpreted Petri nets and implemented in Xilinx FPGA devices. The technique is oriented on further dynamic partial reconfiguration of the system. An adequate splitting algorithm of the system into the dynamic (reconfigurable) and static (non-reconfigurable) partitions is proposed. The main advantage of the presented idea is the possibility of the dynamic reconfiguration of the already implemented system. It means that the functionality of the selected component (module) of the controller can be changed, while the rest of the system is still running. The presented technique is illustrated by a real-life case-study example, and it has been verified experimentally with the application of Xilinx FPGA device.

An online fault injection method for the dynamic partial reconfiguration system based on a lightweight ICAP controller

An online fault injection method for the dynamic partial reconfiguration system based on a lightweight ICAP controller

Low power NoC architecture based dynamic reconfigurable system

The on chip communication intention is difficult due to communication necessities and the difficulty of the objective application is great. Notably, different communication areas might be actualized utilizing a similar chip range, for example, to enable various parallel applications to be stacked onto the device. So the system on chip (SoC) deployed in different topologies with different design parameters to achieve the requirements of the target application. Classical communication methods such as point to point, the bus is not an appropriate solution for future SoCs. That is difficult to send signals starting with one end then onto the next term of a clock cycle. Issues, for example, global wire delay and global synchronization will restrict us. With a specific end goal to beat these problems, architect utilizes new models, procedures, and tools from network design field and apply them to SoCs plan that prompts modern worldview called network on a chip. In this paper, the design components used and the operation of the proposed architecture is same with network on chip (NoC) approach. But it differs in the communication architecture with the introduction of the on-chip peripheral bus. And it differs from the NoC by its switching networks. We modified the switching system that is developed to support dynamically reconfigurable network. Due to this modification in the switching system restrict the area and the power use of the NoC.

FPGA-Based Reconfigurable Data Acquisition System for Industrial Sensors

A sensor data acquisition system is an essential part of an industrial automation control system. However, the variety of sensor producer causes the difficulty of protocol's unity. The mechanism which requires the acquisition boards to be powered off when the number or types or manufacturer of sensors is changed is unreasonable. Meanwhile, traditional sensor reading cycle depends more on the embedded program skills. In this paper, to solve these problems, a new method is proposed to design a reconfigurable data acquisition system for industrial sensors, in which field-programmable gate array (FPGA) is adopted as the core controller. We use both dynamic system reconfiguration and static system reconfiguration in our design. Performance of the proposed system is verified in practical application of an automated production system of poly carboxylic acid water reducing agent.

Energy-aware run-time task partition and allocation in dynamic partial reconfigurable systems

Abstract Dynamic partial reconfigurable systems with a processor and a field-programmable gate array are promising innovations for meeting the requirement of mobile embedded devices. These systems demonstrate low power consumption and high performance. However, with limited battery life and chip size, energy saving and area allocation are critical concerns for such systems. In this study, an energy-aware hardware/software partition is presented to minimize the system energy consumption, and a contention-aware task allocation is presented to minimize the area requirement and response time. The energy efficiency and schedulability of the proposed methodology were evaluated using a series of workloads, and impressive results were obtained.

Generalized Boolean logic Driven Markov Processes: A powerful modeling framework for Model-Based Safety Analysis of dynamic repairable and reconfigurable systems

This paper presents a modeling framework that permits to describe in an integrated manner the structure of the critical system to analyze, by using an enriched fault tree, the dysfunctional behavior of its components, by means of Markov processes, and the reconfiguration strategies that have been planned to ensure safety and availability, with Moore machines. This framework has been developed from BDMP (Boolean logic Driven Markov Processes), a previous framework for dynamic repairable systems. First, the contribution is motivated by pinpointing the limitations of BDMP to model complex reconfiguration strategies and the failures of the control of these strategies. The syntax and semantics of GBDMP (Generalized Boolean logic Driven Markov Processes) are then formally defined; in particular, an algorithm to analyze the dynamic behavior of a GBDMP model is developed. The modeling capabilities of this framework are illustrated on three representative examples. Last, qualitative and quantitative analysis of GDBMP models highlight the benefits of the approach.

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

An empirical comparison of formalisms for modelling and analysis of dynamic reconfiguration of dependable systems

This paper uses a case study to evaluate empirically three formalisms of different kinds for their suitability for the modelling and analysis of dynamic reconfiguration of dependable systems. The requirements on an ideal formalism for dynamic software reconfiguration are defined. The reconfiguration of an office workflow for order processing is described, and the requirements on the reconfiguration of the workflow are defined. The workflow is modelled using the Vienna Development Method (VDM), conditional partial order graphs (CPOGs), and the basic Calculus of Communicating Systems for dynamic process reconfiguration (basic CCSdp), and verification of the reconfiguration requirements is attempted using the models. The formalisms are evaluated according to their ability to model the reconfiguration of the workflow, to verify the requirements on the workflow’s reconfiguration, and to meet the requirements on an ideal formalism.

Partial dynamic reconfiguration framework for FPGAs through remote access

With the advent of internet of things (IoT) and ubiquitous computing, the need for resource aware reconfiguration platform is increasing tremendously. Though a number of dynamic partial reconfiguration systems are available, they consume a significant portion of base system area in comparison with the application running on the system. Larger area requirements of reconfigurable platform cannot take the advantage of reconfigurable systems. Hence, a light weighted and flexible reconfigurable framework with remote access reconfiguration is proposed. The system occupied less than 1% of the total device resources and attained 400 MBps reconfiguration throughput. This framework can be used to any number of reconfiguration regions and is suitable for any application. The proposed framework for partial dynamic reconfiguration through remote access is tested on Virtex 5 XC5VFX70T and Virtex 6 XC6VLX240T FPGAs with 1 Gbps Ethernet link.

Partial dynamic reconfiguration framework for FPGAs through remote access

With the advent of internet of things (IoT) and ubiquitous computing, the need for resource aware reconfiguration platform is increasing tremendously. Though a number of dynamic partial reconfiguration systems are available, they consume a significant portion of base system area in comparison with the application running on the system. Larger area requirements of reconfigurable platform cannot take the advantage of reconfigurable systems. Hence, a light weighted and flexible reconfigurable framework with remote access reconfiguration is proposed. The system occupied less than 1% of the total device resources and attained 400 MBps reconfiguration throughput. This framework can be used to any number of reconfiguration regions and is suitable for any application. The proposed framework for partial dynamic reconfiguration through remote access is tested on Virtex 5 XC5VFX70T and Virtex 6 XC6VLX240T FPGAs with 1 Gbps Ethernet link.

Investigation of system structure and information processing mechanism for cognitive skywave over-the-horizon radar

Based on the cognitive radar concept and the basic connotation of cognitive skywave over-the-horizon radar (SWOTHR), the system structure and information processing mechanism about cognitive SWOTHR are researched. Among them, the hybrid network system architecture which is the distributed configuration combining with the centralized cognition and its soft/hardware framework with the sense-detection integration are proposed, and the information processing frame based on the lens principle and its information processing flow with receive-transmit joint adaption are designed, which build and parse the work law for cognition and its self feedback adjustment with the lens focus model and five stages information processing sequence. After that, the system simulation and the performance analysis and comparison are provided, which initially proves the rationality and advantages of the proposed ideas. Finally, four important development ideas of future SWOTHR toward “high frequency intelligence information processing system” are discussed, which are scene information fusion, dynamic reconfigurable system, hierarchical and modular design, and sustainable development. Then the conclusion that the cognitive SWOTHR can cause the performance improvement is gotten.

A vibration damping optimization algorithm for solving a new multi-objective dynamic cell formation problem with workers training

This paper presents a comprehensive multi-objective mixed integer mathematical programming model which considers cell formation and production planning problems simultaneously. This comprehensive model includes dynamic system reconfiguration, multi period production planning, operation sequence, alternative process plans for part types, machine and worker flexibility, duplicate machines, machine capacity, available time of workers and worker assignment. The aim of the proposed model is to minimize inter and intra-cell movement costs, machine and reconfiguration costs, setup costs, production planning costs (holding, backorder and subcontracting costs) and workers hiring, firing, training and salary costs, as well as minimizing summation of machines idle times as a second objective. Due to NP-hardness of the problem, a recent and efficient meta-heuristic algorithm namely multi-objective vibration damping optimization (MOVDO) is designed for finding Pareto-optimal frontier. In order to check the efficiency of the developed algorithm, it is compared with two salient multi-objective genetic algorithms named NSGAII and NRGA. Finally, by generating some test problems in small and large scales and using some multi-objective comparison metrics, the algorithms are compared and analyzed statistically.

Design of Cellular Manufacturing Systems Considering Dynamic Production Planning and Worker Assignments

This article presents a comprehensive mathematical model for the design and analysis of Dynamic Cellular Manufacturing Systems (DCMS). The proposed DCMS model considers several manufacturing attributes such as multi period production planning, dynamic system reconfiguration, duplicate machines, machine capacity, the available time for workers, worker assignments, and machine procurement. The objective is to minimize total costs; consisting of holding cost, outsourcing cost, inter-cell material handling cost, maintenance and overhead cost, machine relocation cost. While a study of published articles in the area of Cellular Manufacturing Systems (CMS) shows that workforce management issues have not sufficiently been addressed in the literature, the model presented also incorporates CMS workforce management issues such as salaries, hiring and firing costs of workers in addition to the manufacturing attributes. In-depth discussions on the results for two numerical examples are presented to illustrate applications of the proposed model. The model developed aims to raise the envelope by expanding and improving several CMS models previously presented in the literature.

To Propose a Mobility Based Reconfigurable System under Disaster Management in WSN

In this work, it proposes mobility based dynamic reconfiguration system in WSN. In this work, it uses the concept of dynamic reconfiguration routing protocol that achieves the need of various applications and also various network conditions. In this work, an environmental data collection scenario is taken. In this, all nodes are in dynamic nature and moves randomly. All nodes are communicating with each other as well as from head nodes. There is a direct communication between head & nodes. It provides a multi-hop routing based on shortest path in wireless networks. It provides a complete path with the loss of some packets. In this work, a controller is designed which is used to control the movement and location of nodes. Before disaster occurred, all nodes changed their location for security. As disaster under control, there may get back to their locations. But in this, some localization error is present but its value is less than 3% which is very efficient.