Dynamic Hardware Reconfiguration Research Articles

An investigation of performance and power efficiency for parallax background scrolling hardware written in high-level synthesis

We are developing a game programming software library so that high-level synthesis, HLS, can automatically generate high-performance and low-power hardware modules. A mobile terminal with a user-available reconfigurable device like Field programmable gate array, FPGA, we have proposed will efficiently perform game application built in HLS-oriented game library instead of power-hungry software execution. The dynamic hardware reconfiguration on a single FPGA can execute many kinds of game applications. Our previous research has developed software description methods for two-background scrolling in HLS-oriented game programming library by using two methods. They are (1) Full-parallel equips plural physical ports loading background images individually making HLS hardware execute the entire process parallelly increasing the amount of hardware: (2) Semi-parallel shares the single port loading background images serially, suppressing the hardware growth while achieving moderate performance by overlapping operation phases. We investigate two methods about execution time and power efficiency on the parallax scrolling with 2 to 4 backgrounds. The execution times of full-parallel hardware at 100MHz clock frequency are constantly about 9.65 [ms] while those of semi-parallel are 28, 38 and 47 [ms]. The PC at 3.2 GHz shows 78, 98 and 105 [ms] respectively as well. The power efficiencies about the full-parallel estimated considering hardware enlargement are 167, 208 and 112 times compared to the software execution in the PC, while those of semi-parallel are 94, 88 and 75 times. This fact indicates that the full-parallel is better strategy for parallax background scrolling in this case although more hardware resource are invested.

Real-time task scheduling and network device security for complex embedded systems based on deep learning networks

As a hotspot of machine learning research, deep learning is applied in many fields. Embedded systems are becoming more and more complex and networked, so the real-time performance of embedded systems and the security of network embedded devices face severe challenges. Based on this, this paper studies the real-time task scheduling problem for complex embedded systems and the security of embedded network devices. For real-time, this paper proposes a comprehensive task scheduling algorithm. Based on the task classification in the embedded system, different scheduling methods are adopted for different tasks, and the scheduling mode is flexibly changed as the system load changes. A dynamic integrity measurement model is established based on the star trust chain structure, and the hardware implementation mechanism of constructing dynamic trust chain in embedded system is studied. The dynamic reconfigurable hardware design method based on FPGA is applied to the construction of dynamic trust chain, and a verification system is designed to verify the dynamic measurement mechanism. This can solve the security problem of deep network embedded devices to a certain extent.

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA’s many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device’s security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency. In this research work, we introduce novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices. We also introduce unique system-level architectures for our proposed designs. To the best of our knowledge, no similar work exists in the literature that provides dynamic and partial reconfigurable hardware for SPECK and SIMON, and also provides system-level architecture. Our dynamic and partial reconfigurable hardware designs achieve 28% space saving compared to its static reconfigurable hardware, and 59 times speedup compared to its software counterpart.

A reconfigurable hardware platform for low-power wide-area wireless sensor networks

Low power, large-area wireless sensor networks (WSNs) have been experiencing rapid growth in a wide range of applications, such as environmental monitoring applications and natural disaster early warning systems. The WSN consists of numerous nodes with sensing, computation, actuation, and radio communication capabilities. Dynamically reconfigurable hardware and context-aware operation to optimize performance and functionality and to prolong the lifetime of sensor nodes are critical goals in the design of distributed sensing systems, especially for battery-based systems being deployed in complex geographic areas where are hard to approach. In recent years, Programmable System-on-Chip (PSoC) technology is emerging as an efficient solution for achieving the dynamic hardware reconfiguration of a sensor node in a single chip. That aims at optimizing the use of resources, minimizing of energy waste, and system size according to the requirements of the applications. This paper presents the implementation of a configurable hardware platform for remote sensing systems based on PSoC and LoRa technology. The proposed hardware design stands out for high performance, ultralow-power, providing long-range communication as well as reconfigurable interfaces in communicating and manipulating with various types of sensors and actuators. The experiments to evaluate the functional requirements and energy consumption of the design were investigated with positive results.

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware

With the proliferation of mobile/embedded devices, multiple running applications are becoming a necessity on these devices. Thus, state-of-the-art techniques are needed to support complex applications running on mobile systems. We envision in the near future, many mobile devices will be implemented/delivered on FPGA-based reconfigurable chips. Previous analysis illustrated that FPGA-based dynamic-reconfigurable-hardware is currently the best option to deliver embedded applications that have stringent requirements. However, computation models and application characteristics play significant roles in determining whether this hardware is indeed a good match for specific embedded applications. Furthermore, selecting a specific dynamic reconfiguration method (out of many) and designing the corresponding hardware architectures for an application are important and challenging tasks. This paper proposes a design methodology for FPGA-based dynamic-reconfigurable-hardware that provides guidelines in mapping application's computation models and characteristics to the most suitable reconfiguration methods. Pipelined and functional-parallel models are used as case studies to illustrate the design methodology.

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware

With the proliferation of mobile/embedded devices, multiple running applications are becoming a necessity on these devices. Thus, state-of-the-art techniques are needed to support complex applications running on mobile systems. We envision in the near future, many mobile devices will be implemented/delivered on FPGA-based reconfigurable chips. Previous analysis illustrated that FPGA-based dynamic-reconfigurable-hardware is currently the best option to deliver embedded applications that have stringent requirements. However, computation models and application characteristics play significant roles in determining whether this hardware is indeed a good match for specific embedded applications. Furthermore, selecting a specific dynamic reconfiguration method (out of many) and designing the corresponding hardware architectures for an application are important and challenging tasks. This paper proposes a design methodology for FPGA-based dynamic-reconfigurable-hardware that provides guidelines in mapping application's computation models and characteristics to the most suitable reconfiguration methods. Pipelined and functional-parallel models are used as case studies to illustrate the design methodology.

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

Dynamic Reconfigurable Hub as a Stationary Node in a Hybrid Sensor Network

Sensor network systems are being expanded with the development of technology for the design of a low-power chips and for operating sensor networks. However, it is difficult to modify or change an application for a stationary sensor node after installation in the field. Furthermore, there is a limit to installation after developing and testing a new sensor node if it needs to reconfigure the software and hardware of the existing sensor node. Therefore, not only is software reconfiguration needed but also dynamic hardware reconfiguration for various changes in requirements, such as sensor type, communication bandwidth, quality of service, or reduced power consumption depending on the changing environment and requirements of users. This paper proposes a specially designed stationary node called a SMART (system management architecture for reconfigurable technology) node, which is capable of dynamic reconfiguration of the various sensing functions or communication protocols. The SMART node can provide suitable service and change the communication protocol according to various surroundings and user requirements.

Implementation of Dynamically Reconfigurable Systems on Chip with OS Support

This work presents the implementation of dynamically reconfigurable system with operating system support specifically Linux. The presented work combines both HW and SW flows where the complex parts of the architecture are designed to HW modules. These HW modules can be reconfigured on the fly by using partial dynamic reconfiguration. In our work, we are using floating point computation unit as partial reconfiguration module. Our aim is to show the idea how an operating system can be involved in the area of reconfiguration computing. The application that manages the reconfiguration can be developed either as standalone software that is specific for the system or with an operating system support, to achieve code reusability and code portability. Finally, a prototype is implemented on Xilinx ML507 board, where a general Linux open source kernel has been used to handle dynamic reconfigurable hardware recourses.

Using Data Contention in Dual-ported Memories for Security Applications

Field Programmable Gate Arrays (FPGA) provide the invaluable feature of dynamic hardware reconfiguration by loading configuration bit files. However, this flexibility also opens up the threat of theft of Intellectual Property (IP) since these configuration files can be easily extracted and cloned. In this context, the ability to bind an application configuration to a specific device is an important step to prevent product counterfeiting. Furthermore, such a technology can also enable advanced business models such as device-specific feature activation. In this work, we present a new technique to generate entropy on FPGA device--based on data contention in the hardware circuitry. For this entropy, we use the output of intentionally generated write collisions in synchronous dual-ported block RAMs (BRAM). We show that the parts of this output generated by such write collisions can be either probabilistic but also deterministic and device-specific. The characteristics of such an entropy source can be used for a large variety of security applications, such as chip identification and device authentication. In addition to that, we also propose a solution to efficiently create cryptographic keys on-chip at runtime. As a last contribution, we eventually present a strategy how to transform this entropy source into a circuit for True Random Number Generation (TRNG).

Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems

Reconfigurable architectures are increasingly often applied in various industrial data processing applications, due to the possibility for performing parallel computations and achieving a simplified Systemon-Chip design flow. Furthermore, the exploitation of dynamic and partial hardware reconfiguration has been investigated in different research projects, often in systems based on Xilinx Virtex 2/4 FPGA families, by time-multiplexing hardware resources for multiple functions. This paper describes the exploitation of partial reconfiguration for dynamic power management in a low-power Spartan 3-based level measurement application. The reconfiguration process is thereby applied to optimize system implementation according to the applications requirements on power consumption and performance.

Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)

Reconfigurable devices in large complex systems allow the reduction of the amount of required resources. They serve as run-time re-usable devices for performance critical data-oriented processes. However, the use of reconfigurable devices within large systems greatly increases the design complexity. The designer´s task gets even harder when the goal is a resource efficient solution. Constructing a good design requires the consideration of many design alternatives. With today´s complex systems and the resulting degrees of freedom the designer should be assisted by sophisticated design space exploration tools. However, all known system-level design space exploration tools do not exploit the potentials dynamic hardware reconfiguration exposes. Moreover, the implementation of selected solutions poses an additional challenge and also requires a cycle-level simulation. This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level design space exploration.

New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)

A new dynamic reconfigurable hardware architecture, the HoneyComb, will be introduced that has been developed within the project AMURHA. New integrated features enhance the flexibility and usability of future array-based systems by exploring the new approach.

Server-based execution of periodic tasks on dynamically reconfigurable hardware

A prototype system that executes a set of periodic real-time tasks utilising dynamic hardware reconfiguration is presented. The proposed scheduling technique, merge server distribute load (MSDL), is not only able to give an offline guarantee for the feasibility of the task set, but also minimises the number of device configurations. After describing this technique, the schedulability analysis is extended to cover different runtime system overheads, including the device reconfiguration time. Then, a light-weight runtime system that performs the online part of the MSDL scheduling technique is detailed. The runtime system is implemented entirely in hardware. Finally, the corresponding synthesis tool flow is outlined and the overhead posed by the runtime system is reported.

An overview of configurable computing machines for software radio handsets

The advent of software radios has brought a paradigm shift to radio design. A multimode handset with dynamic reconfigurability has the promise of integrated services and global roaming capabilities. However, most of the work to date has been focused on software radio base stations, which do not have as tight constraints on area and power as handsets. Base station software radio technology progressed dramatically with advances in system design, adaptive modulation and coding techniques, reconfigurable hardware, A/D converters, RF design, and rapid prototyping systems, and has helped bring software radio handsets a step closer to reality. However, supporting multimode radios on a small handset still remains a design challenge. A configurable computing machine, which is an optimized FPGA with application-specific capabilities, show promise for software radio handsets in optimizing hardware implementations for heterogeneous systems. In this article contemporary CCM architectures that allow dynamic hardware reconfiguration with maximum flexibility are reviewed and assessed. This is followed by design recommendations for CCM architectures for use in software radio handsets.

Low Power Encoding Techniques for Dynamically Reconfigurable Hardware

In this paper, an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to automatically minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 41%.

Reconfigurable hardware implementation of BinDCT

Enhancing the coding gain and operand throughput of a data compression application through dynamic hardware reconfiguration is described. A novel implementation of the BinDCT, a discrete cosine transform (DCT) approximation has been realised on a run-time reconfigurable custom XC6200 field programmable gate array-based dynamic coprocessor, coupled to a TMS320C40 digital signal processor system.

Formally Analyzed Dynamic Synthesis of Hardware

Dynamic hardware reconfiguration based on run-time system specialization is viable with FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesis algorithm used to reconfigure FPGA designs at run-time. The verification approach is based on a deep embedding of a language for netlist and the relational hardware modeling style.