Dynamic Random Access Memory Chips Research Articles

DRAM Retention Behavior with Accelerated Aging in Commercial Chips

The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error.

OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems.

With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current solution still suffers from high overhead when a large DRAM capacity is used to deliver high performance. We present a DRAM chip architecture that can track faults at byte-level DRAM cell errors to address this problem. DRAM faults are classified as temporary or permanent in our proposed architecture, with no additional pins and with minor DRAM chip modifications. Hence, we achieve reliability comparable to that of other state-of-the-art solutions while incurring negligible performance and energy overhead. Furthermore, the faulty locations are efficiently exposed to the operating system (OS). Thus, we can significantly reduce the required scrubbing cycle by scrubbing only faulty DRAM pages while reducing the system failure probability up to 5000∼7000 times relative to conventional operation.

Demystifying Complex Workload-DRAM Interactions

It has become increasingly difficult to understand the complex interactions between modern applications and main memory, composed of Dynamic Random Access Memory (DRAM) chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, memory access patterns of prevalent and emerging applications are rapidly diverging, as these applications manipulate larger data sets in very different ways. As a result, the combined DRAM-workload behavior is often difficult to intuitively determine today, which can hinder memory optimizations in both hardware and software. In this work, we identify important families of workloads, as well as prevalent types of DRAM chips, and rigorously analyze the combined DRAM-workload behavior. To this end, we perform a comprehensive experimental study of the interaction between nine different DRAM types and 115 modern applications and multiprogrammed workloads. We draw 12 key observations from our characterization, enabled in part by our development of new metrics that take into account contention between memory requests due to hardware design. Notably, we find that (1) newer DRAM technologies such as DDR4 and HMC often do not outperform older technologies such as DDR3, due to higher access latencies and, also in the case of HMC, poor exploitation of locality; (2) there is no single memory type that can effectively cater to all of the components of a heterogeneous system (e.g., GDDR5 significantly outperforms other memories for multimedia acceleration, while HMC significantly outperforms other memories for network acceleration); and (3) there is still a strong need to lower DRAM latency, but unfortunately the current design trend of commodity DRAM is toward higher latencies to obtain other benefits. We hope that the trends we identify can drive optimizations in both hardware and software design. To aid further study, we open-source our extensively-modified simulator, as well as a benchmark suite containing our applications.

Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation

Refresh power of dynamic random-access memory (DRAM) has become a critical problem due to the large memory capacity of servers and mobile devices. It is imperative to reduce refresh rate in order to reduce refresh power consumption. However, current methods of refresh rate improvement have limitations such as large area/performance overhead, low system availability, and lack of support at the memory controller. We propose a novel scheme which comprises three essential functions: (1) an adaptive refresh method that adjusts refresh period on each DRAM chip, (2) a runtime method of retention-time profiling that operates inside DRAM chips during idle time thereby improving availability, and (3) a dual-row activation method which improves weak cell retention time at a very small area cost. The proposed scheme allows each DRAM chip to refresh with its own refresh period without requiring the external support. Experiments based on real DRAM chip measurements show that the proposed methods can increase refresh period by 4.5 times at 58 °C by adjusting refresh period in a temperature-aware manner while incurring only a small overhead of 1.05% and 0.02% in DRAM chip area and power consumption, respectively. Below 58 °C, our method improves the refresh period by 12.5% compared with two state-of-the-art methods, AVATAR and in-DRAM ECC. In various memory configurations with SPEC benchmarks, our method outperforms the existing ones in terms of energy-delay product by 19.7% compared with the baseline, and by 15.4% and 12.4%, with respect to AVATAR and in-DRAM ECC, respectively.

RowHammer: A Retrospective

This retrospective paper describes the RowHammer problem in dynamic random access memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 Conference. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors , which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology. Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this paper, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or phase change memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities.

Firm’s Responsive Behaviours in WTO Trade Disputes: Countervailing Cases on Korean DRAMs

How do decisions of the World Trade Organization (WTO) Dispute Settlement Body (DSB) relate to economic/trade gains? This is an important question to consider when evaluating the efficacy of the WTO DSB. Although it may seem obvious that a successful dispute resolution through the DSB would remove trade barriers and increase trade, the ruling effects are not so straightforward, with recent empirical studies suggesting an unclear causality between the dispute resolutions and subsequent changes in trade. Using product and firm-level data, this article examines three WTO disputes over countervailing duties on Korean Dynamic Random Access Memory chips, which have raised similar legal issues but yielded different outcomes. By investigating the dynamics of firm behaviour over the course of disputes, our analysis sheds light on the difficulties of detecting changes in trade flows following rulings by the DSB. We conclude that cross-border trade flows are substantially affected by firm-and-market specific adjustments interacting with the current world trade environment, such as flexible reallocation of resources and promotion of a production network.

Novel Method for Nondestructive Body Effect Measurement in Dynamic Random Access Memory

Body effect is a key characteristic of a dynamic random access memory (DRAM) cell transistor. The conventional method uses a test element structure or nano-probe equipment for body effect measurements. However, the test element structure measurement is inaccurate because the structure is located outside the DRAM chip. Additionally, the nano-probe destroys the chip while measuring the body effect in the chip. Therefore, we developed a novel nondestructive method to measure the body effect in the DRAM. This method uses a memory bitmap test system. The test system was originally a device that determines pass or fail of the cells. However, it was modified to extract the gate voltage that causes the failure due to a cell transistor leakage current. Because the leakage current is correlated to the threshold voltage, this gate voltage is a relative threshold voltage. The body effect was obtained by measuring the relative threshold voltage under different body biases. After confirming the method in a single cell, we simplified the method for a mass cell measurement. Two relative threshold voltages for each body bias were used for a fast and simple test. The mass measurement method could obtain 8196 body cell effects within 2 min. The results of the newly developed method were the same as that of the conventional test element structure measurement.

Understanding and Improving the Latency of DRAM-Based Memory Systems

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems. Increasing core counts, and the emergence of increasingly more data-intensive and latency-critical applications further stress the importance of providing low-latency memory accesses. In this dissertation, we identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we present a series of new techniques. Our new techniques significantly improve both system performance and energy efficiency. We also examine the critical relationship between supply voltage and latency in modern DRAM chips and develop new mechanisms that exploit this voltage-latency trade-o to improve energy efficiency. First, while bulk data movement is a key operation in many applications and operating systems, contemporary systems perform this movement inefficiently, by transferring data from DRAM to the processor, and then back to DRAM, across a narrow o -chip channel. The use of this narrow channel for bulk data movement results in high latency and high energy consumption. This dissertation introduces a new DRAM design, Low-cost Inter-linked SubArrays (LISA), which provides fast and energy-efficient bulk data movement across sub- arrays in a DRAM chip. We show that the LISA substrate is very powerful and versatile by demonstrating that it efficiently enables several new architectural mechanisms, including low-latency data copying, reduced DRAM access latency for frequently-accessed data, and reduced preparation latency for subsequent accesses to a DRAM bank. Second, DRAM needs to be periodically refreshed to prevent data loss due to leakage. Unfortunately, while DRAM is being refreshed, a part of it becomes unavailable to serve memory requests, which degrades system performance. To address this refresh interference problem, we propose two access-refresh parallelization techniques that enable more overlap- ping of accesses with refreshes inside DRAM, at the cost of very modest changes to the memory controllers and DRAM chips. These two techniques together achieve performance close to an idealized system that does not require refresh. Third, we find, for the first time, that there is significant latency variation in accessing different cells of a single DRAM chip due to the irregularity in the DRAM manufacturing process. As a result, some DRAM cells are inherently faster to access, while others are inherently slower. Unfortunately, existing systems do not exploit this variation and use a fixed latency value based on the slowest cell across all DRAM chips. To exploit latency variation within the DRAM chip, we experimentally characterize and understand the behavior of the variation that exists in real commodity DRAM chips. Based on our characterization, we propose Flexible-LatencY DRAM (FLY-DRAM), a mechanism to reduce DRAM latency by categorizing the DRAM cells into fast and slow regions, and accessing the fast regions with a reduced latency, thereby improving system performance significantly. Our extensive experimental characterization and analysis of latency variation in DRAM chips can also enable development of other new techniques to improve performance or reliability. Fourth, this dissertation, for the first time, develops an understanding of the latency behavior due to another important factor { supply voltage, which significantly impacts DRAM performance, energy consumption, and reliability. We take an experimental approach to understanding and exploiting the behavior of modern DRAM chips under different supply voltage values. Our detailed characterization of real commodity DRAM chips demonstrates that memory access latency reduces with increasing supply voltage. Based on our characterization, we propose Voltron, a new mechanism that improves system energy efficiency by dynamically adjusting the DRAM supply voltage based on a performance model. Our extensive experimental data on the relationship between DRAM supply voltage, latency, and reliability can further enable developments of other new mechanisms that improve latency, energy efficiency, or reliability. The key conclusion of this dissertation is that augmenting DRAM architecture with simple and low-cost features, and developing a better understanding of manufactured DRAM chips together leads to significant memory latency reduction as well as energy efficiency improvement. We hope and believe that the proposed architectural techniques and detailed experimental data on real commodity DRAM chips presented in this dissertation will enable developments of other new mechanisms to improve the performance, energy efficiency, or reliability of future memory systems.

Research progresses of dynamic random access memory devices

In this paper, the dynamic random access memory (DRAM) cell technology is introduced and the important technological breakthroughs are reviewed. The criteria of DRAM memory cell design is discussed and the key fabrication technologies of 6F2 memory cell and stack capacitor DRAM cell are summarized. The technological evolution of array access transistor is also reviewed. The transistors with U-shaped transistor or FinFET and the fabrication process flow of 6F2 DRAM chip were discussed. Based upon the technical requirements for DRAM cell, the possible device technologies for the next generation DRAM cell was summarized. It is predicted that (1) U-shape channel transistor will be the mainstream technology for the future DRAM cell beyond 20 nm; (2) low k material will be required for decreasing the bitline parasitic capacitance; (3) sense-amplifier with better signal-noise margin will be required to ease the requirement of high aspect-ratio storage capacitance; (4) low power DRAM design will draw more attention, rather than increasing the storage capacity of DRAM.

Roles of Residual Stress in Dynamic Refresh Failure of a Buried-Recessed-Channel-Array Transistor (B-CAT) in DRAM

We clarify the role of metal gates (e.g., TiN) on the degradation of the state-of-the-art buried-channel-array transistor (B-CAT) in dynamic random access memory (DRAM) chips. Unless the thermal budget during the processing step for integration is well controlled, residual stress caused by grain growth of the metal gate can result in a dynamic refresh failure of B-CAT through the negative shift in threshold voltage ( $- \Delta \text{V}_{\mathrm {th}})$ . A hole trapping model is proposed to explain this phenomenon. Uncontrolled grain growth of the metal gate increases the residual stress level on SiO2, and, consequently, it breaks the strained Si–O–Si bonds, which can serve as precursor sites for incoming holes. Residual stress in the three-dimensional transistor architecture, therefore, must be well controlled to improve the reliability of commercial DRAM chips.

Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-Power Refresh

Dynamic random access memory (DRAM) requires periodic refresh operations to retain its data. In practice, DRAM retention times are normally distributed from 64 ms to several seconds. However, the conventional refresh method uses 64 ms as the refresh interval, since it applies the same refresh interval to all DRAM rows. Thus, the conventional refresh method results in unnecessary refresh operations (eventually, energy waste) to the DRAM rows whose retention times are longer than 64 ms. In this paper, we propose a practical refresh scheme that exploits refresh effect of DRAM read operations to reduce refresh overhead. Our proposed scheme applies a refresh interval longer than the conventional refresh interval (64 ms) to the DRAM chip. In this case, weak DRAM rows (DRAM rows whose retention times are shorter than the refresh interval of the DRAM chip) cannot retain their data. In order to retain the data stored in the weak DRAM rows, the memory controller issues read operations to the weak DRAM rows every required refresh interval for the weak DRAM rows. Our evaluation results show that our proposed scheme with 192 ms refresh interval reduces average refresh energy consumption up to 66.0 percent, which in turn reduces average DRAM energy consumption up to 31.8 percent, compared to the conventional refresh method (64 ms). Our proposed scheme requires no modification to internal DRAM chip structures, but it only adds a small weak row buffer (the buffer for the weak row information) to the memory controller, which has a negligible area overhead.

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

Battling borked bits

Not long after the first personal computers started entering people's homes, Intel fell victim to a nasty kind of memory error. The company, which had commercialized the very first dynamic random-access memory (DRAM) chip in 1971 with a 1,024-bit device, was continuing to increase data densities. A few years later, Intel's then cutting-edge 16-kilobit DRAM chips were sometimes storing bits differently from the way they were written. Indeed, they were making these mistakes at an alarmingly high rate. The cause was ultimately traced to the ceramic packaging for these DRAM devices. Trace amounts of radioactive material that had gotten into the chip packaging were emitting alpha particles and corrupting the data.

Reducing DRAM refreshing in an error correction manner

Dynamic random access memory (DRAM) is facing the challenge of technology scaling. The de-creasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. There-fore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer (ECP), an error-correction-manner framework, to reduce DRAM re-freshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70% refreshing operations than the current refreshing mechanism and also get significant energy saving.

Highly Productive Process Technologies of Cantilever-type Microprobe Arrays for Wafer Level Chip Testing

This paper describes the highly productive process technologies of microprobe arrays, which were used for a probe card to test a Dynamic Random Access Memory (DRAM) chip with fine pitch pads. Cantilever-type microprobe arrays were fabricated using conventional micro-electro-mechanical system (MEMS) process technologies. Bonding material, gold-tin (Au-Sn) paste, was used to bond the Ni-Co alloy microprobes to the ceramic space transformer. The electrical and mechanical characteristics of a probe card with fabricated microprobes were measured by a conventional probe card tester. A probe card assembled with the fabricated microprobes showed good x-y alignment and planarity errors within <TEX>${\pm}5{\mu}m$</TEX> and <TEX>${\pm}10{\mu}m$</TEX>, respectively. In addition, the average leakage current and contact resistance were approximately 1.04 nA and 0.054 ohm, respectively. The proposed highly productive microprobes can be applied to a MEMS probe card, to test a DRAM chip with fine pitch pads.

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 °C for 2 min and thinned down to 30-μm thickness. The DRAM cell characteristics, which show 50% failure at 200 μs, were not degraded from the packaged sample (prethinning) even after chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 °C. Meanwhile, the DRAM cell array shows 50% failure at 70 μs after an intentional Cu diffusion from the backside surface for 30 min at 300 ° C. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface in active areas and cause functional failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no significant change even after Cu diffusion. The on-current performance characterized by majority carriers is not an effective criterion to characterize sensitively the Cu contamination effect.

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.

A Low-&lt;i&gt;V&lt;sub&gt;t&lt;/sub&gt;&lt;/i&gt; Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing

A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4ns and read access (tAA) of 14.3ns at array voltage of 0.9V.

A Mechanism for Dependence of Refresh Time on Data Pattern in DRAM

We measured the refresh time (tREF) according to data patterns for several dynamic random access memory (DRAM) chips. The measured tREF depends on the cell data pattern; moreover, these have their own dependences, which differ for several DRAM chips. We analyzed these phenomena in terms of both refresh and offset measurements, and our novel result was that tREF dependence on data patterns is determined by both a cell leakage mechanism and an offset by sensing noise.

Pricing Abuses by Essential Patent Holders in a Standard-Setting Context: A View from Europe

Pricing Abuses by Essential Patent Holders in a Standard-Setting Context: A View from Europe