Roles of Residual Stress in Dynamic Refresh Failure of a Buried-Recessed-Channel-Array Transistor (B-CAT) in DRAM

Abstract

We clarify the role of metal gates (e.g., TiN) on the degradation of the state-of-the-art buried-channel-array transistor (B-CAT) in dynamic random access memory (DRAM) chips. Unless the thermal budget during the processing step for integration is well controlled, residual stress caused by grain growth of the metal gate can result in a dynamic refresh failure of B-CAT through the negative shift in threshold voltage ( $- \Delta \text{V}_{\mathrm {th}})$ . A hole trapping model is proposed to explain this phenomenon. Uncontrolled grain growth of the metal gate increases the residual stress level on SiO2, and, consequently, it breaks the strained Si–O–Si bonds, which can serve as precursor sites for incoming holes. Residual stress in the three-dimensional transistor architecture, therefore, must be well controlled to improve the reliability of commercial DRAM chips.