Dynamic Random Access Memory Research Articles

A high-performance capacitorless 1T-DRAM based on Z-shaped electron-hole bilayer TFET and SiGe memory window

Abstract In this paper, a novel capacitorless dynamic random access memory (Z-EHBTFET 1T-DRAM) is designed based on a Z-shaped electron-hole bilayer tunnel field-effect transistor and a SiGe memory window, and its storage performance is systematically analyzed and studied in detail through numerical simulation. A large number of electrons can be induced in the inverted L-shaped channel of Z-EHBTFET 1T-DRAM using gate 1 to create an electron-hole bilayer together with the source region, which increases the line tunneling electric field and ultimately improves the sensing margin (SM) and read current ratio (IR1/IR0). SiGe memory window helps to improve the storage capacity of holes, aiming to improve the retention time (RT) and SM. By optimizing the Ge-composition and width of the SiGe memory window, the thickness of the I-shaped channel, and the gate gap length, the SM of 2.03 μA/μm, IR1/IR0 of 3.58 × 104, and RT of 1.2 s can be obtained for Z-EHBTFET 1T-DRAM. Compared with most reported 1T1C-DRAMs and traditional 1T-DRAMs, it has better storage performance. Moreover, it can operate at a lower programming voltage while ensuring superior storage performance, making it has great application prospect in the low power consumption field.

Effect of Al doping on structural and electrical properties of HfO2/ZrO2 layered structures for high-k applications

ZrO2 films with ultrathin Al2O3 layers have effectively contributed to the miniaturization of dynamic random access memory (DRAM) capacitors for many years. However, as memory devices continue to shrink, higher dielectric constants are required to maintain cell capacitance. To address this challenge, research has explored the use of tetragonal HfO2 layers, which theoretically possess a higher dielectric constant than ZrO2, as dielectrics. However, the thermodynamically stable phase of HfO2 is monoclinic with a lower dielectric constant, necessitating a phase transition to the tetragonal form for DRAM capacitor applications. Although attempts have been made to induce this phase transition to achieve high dielectric constants by applying an HfO2/ZrO2 layered structure or doping HfO2 with elements such as Zr, Al, and Si, significant challenges remain in completely eliminating the monoclinic phase or implementing a pure tetragonal phase of HfO2. In this study, we systematically investigated the crystallinity changes and improved the electrical properties of HfO2/ZrO2 layered structures with Al doping in the HfO2 layers. Our findings demonstrate that optimizing the partitioning of the ZrO2 and HfO2 layers, combined with Al doping, effectively achieves equivalent oxide thickness scaling.

A Novel 3D 2TnC FeRAM Architecture and Operation Scheme with Improved Disturbance for High-Bit-Density Dynamic Random-Access Memory

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string.

High performance Si-MoS2 heterogeneous embedded DRAM

Embedded Dynamic RAM (eDRAM) has become a key solution for large-capacity cache in high-performance processors. A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS2) is reported to address the short retention issue in conventional gain cell (GC) eDRAMs meanwhile eliminate the pillar capacitor in one transistor and one capacitor (1T1C) eDRAMs. The MoS2 write transistor with low OFF current (IOFF) enables long data retention, while the Si read transistor offers high drive current and logic compatibility. This combination enhances data retention by 1000 times and sense margin by 100 times respectively compared to full Si and MoS2 counterparts. A three-dimensional (3D) design stacking MoS2 on Si is demonstrated with back-end-of-line (BEOL) process to double integration density. With 6000 s data retention, 35 μA/μm sense margin, 5 ns access speeds, 3D integration and CMOS logic compatibility, this Si-MoS2 eDRAM marks a significant advancement in memory technology.

SPIRIT: Scalable and Persistent In-Memory Indices for Real-Time Search

Today, real-time search over big microblogging data requires low indexing and query latency. Online services, therefore, prefer to host inverted indices in memory. Unfortunately, as datasets grow, indices grow proportionally, and with limited DRAM scaling, the main memory faces high pressure. Also, indices must be persisted on disks as building them is computationally intensive. Consequently, it becomes necessary to frequently move on-heap index segments to storage, slowing down indexing. Reading storage-resident index segments requires filesystem calls and disk accesses during query evaluation, leading to high and unpredictable tail latency. This work exploits hybrid DRAM and scalable non-volatile memory (NVM) to offer dynamically growing and instantly searchable (i.e., real-time) persistent indices in on-heap memory. We implement SPIRIT, a real-time text inversion engine over hybrid memory. SPIRIT exploits the byte-addressability of hybrid memory to enable direct access to the index on a pre-allocated heap, eliminating expensive block storage accesses and filesystem calls during live operation. It uses an in-memory segment descriptor table to offer: ① instant segment availability to query evaluators upon fresh ingestion, ② low-overhead segment movement across memory tiers transparent to query evaluators, and ③ decoupled segment movement into NVM from their visibility to query evaluators, enabling different policies for mitigating NVM latency. SPIRIT accelerates compaction with zero-copy merging. It supports volatile, graceful shutdown, and crash-consistent indexing modes. The latter two modes offer instant recovery using persistent pointers. SPIRIT with hybrid memory and strong crash consistency guarantees exhibits many orders of magnitude better tail response times and query throughout than the state-of-the-art Lucene search engine. Compared against a highly optimized non-real-time evaluation of Lucene with liberal DRAM size, on average, across six query workloads, SPIRIT still delivers 2.5 × better (real-time) query throughput. Our work applies to other services that will benefit from direct on-heap access to large persistent indices.

Enhanced Oxidation Resistance and Interface Stability of Atomic-Layer-Deposited MoNx Electrodes via TiN Passivation for DRAM Cell Capacitor Applications.

The continuous miniaturization of dynamic random-access memory (DRAM) capacitors has amplified the demand for electrode materials featuring specific characteristics, such as low resistivity, high work function, chemical stability, excellent interface quality with high-k dielectrics, and superior mechanical properties. In this study, molybdenum nitride (MoNx) films were deposited using a plasma-enhanced atomic layer deposition (PEALD) employing bis(isopropylcyclopentadienyl)molybdenum(IV) dihydride and NH3 plasma for DRAM capacitor electrode applications. Depending on the deposition temperatures of the PEALD MoNx films ranging from 200 to 400 °C, the Mo/N ratio and crystal structure varied, transitioning from the cubic NaCl-B1-type MoN phase with Mo/N ratio of 1.4 to the cubic γ-Mo2N phase with Mo/N ratio of 1.9. Notably, MoNx films grown at 400 °C exhibited low resistivity (435 μΩ·cm), a high work function (5.28 eV), and superior mechanical hardness (11.3 GPa) compared to ALD TiN films. Despite these excellent properties, the PEALD MoNx electrode demonstrated insufficient chemical stability, particularly in terms of oxidation resistance and interface quality with ALD HfxZr1-xO2 (HZO) films. This resulted in poor morphology and the formation of significant oxygen-deficient HZO layers (such as HfO2-x), leading to considerable degradation in the electrical performance of metal-insulator-metal (MIM) capacitors. To mitigate this issue, a thin (2.5-14 nm) ALD TiN layer was introduced as a passivation layer between the MoNx bottom electrode and HZO dielectric. The TiN-passivated MoNx (TiN/MoNx) electrode showed substantially enhanced oxidation resistance and reduced interfacial reactions with the HZO dielectric. Consequently, MIM capacitors with TiN/MoNx bottom electrodes demonstrated outstanding electrical performance, including excellent dielectric properties, low leakage current density, and high mechanical strength. Hence, this study proposes a promising candidates for storage nodes in the next-generation DRAM capacitors.

Schottky barrier memory based on heterojunction bandgap engineering for high-density and low-power retention

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

QM-ARC: QoS-aware Multi-tier Adaptive Cache Replacement Strategy

Distributed data-centric systems, such as Named Data Networking, utilize in-network caching to reduce application latency by buffering relevant data in high-speed memory. However, the significant increase in data traffic makes expanding memory capacity prohibitively expensive. To address this challenge, integrating technologies like non-volatile memory and high-speed solid-state drives with dynamic random-access memory can form a cost-effective multi-tier cache system. Additionally, most existing caching policies focus on categorizing data based on recency and frequency, overlooking the varying Quality-of-Service (QoS) requirements of applications and customers—a concept supported by Service Level Agreements in various service delivery models, particularly in Cloud computing. One of the most prominent algorithms in caching policy literature is the Adaptive Replacement Cache (ARC), that uses recency and frequency lists but does not account for QoS. In this paper, we propose a QoS-aware Multi-tier Adaptive Replacement Cache (QM-ARC) policy. QM-ARC extends ARC by incorporating QoS-based priorities between data applications and customers using a penalty concept borrowed from service-level management practices. QM-ARC is generic, applicable to any number of cache tiers, and can accommodate various penalty functions. Furthermore, we introduce a complementary feature for QM-ARC that employs Q-learning to dynamically adjust the sizes of the two ARC lists. Our solution, evaluated using both synthetic and real-world traces, demonstrates significant improvements in QoS compared to state-of-the-art methods by better considering priority levels. Results show that QM-ARC reduces penalties by up to 45% and increases the hit rate for high priority data by up to 84%, without negatively impacting the overall hit rate, which also increases by up to 61%.

SSA-over-array (SSoA): A stacked DRAM architecture for near-memory computing

Aiming to enhance the bandwidth in near-memory computing, this paper proposes a SSA-over-array (SSoA) architecture. By relocating the secondary sense amplifier (SSA) from dynamic random access memory (DRAM) to the logic die and repositioning the DRAM-to-logic stacking interface closer to the DRAM core, the SSoA overcomes the layout and area limitations of SSA and master DQ (MDQ), leading to improvements in DRAM data-width density and frequency, significantly enhancing bandwidth density. The quantitative evaluation results show a 70.18 times improvement in bandwidth per unit area over the baseline, with a maximum bandwidth of 168.296 Tbps/Gb. We believe the SSoA is poised to redefine near-memory computing development strategies.

A Better Sense Amplifier Improves the Resilience in Compute-In-Memory and Row Hammer

As machine learning (ML) workloads continue to scale, the demand for higher-density DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory) is intensifying, and also driving interest in compute-in-memory (CIM) architectures as a promising approach to enhancing computational efficiency. However, increasing DRAM cell density introduces significant challenges, particularly in the reliable identification of charge sharing between cells and bit lines. This challenge heightens the susceptibility of DRAM to row hammer attacks, where unintended data corruption occurs due to repeated access to adjacent rows. Furthermore, CIM architectures necessitate more precise sensing of bit lines to ensure accurate computation within memory. In light of these challenges, our study proposes an investigation into the potential benefits of utilizing an offset compensation sense amplifier (OCSA). The OCSA is designed to address the accuracy limitations posed by high-density DRAM in CIM applications. By enhancing the precision of bit line sensing, the OCSA may mitigate the vulnerability to row hammer attacks and improve the overall reliability and performance of CIM architectures. This study will explore the effectiveness of the OCSA in maintaining data integrity and computational accuracy within high-density DRAM environments, offering insights into its applicability for future ML workloads.

Python-Based DRAM Memory Controller Testbench: Pyuvm an Early Report

With Hardware Verification being regarded as a time-consuming complex task. Moreover, new design applications Such as machine learning are posing new challenges to hardware verification engineers. Adding on top of the above challenges the fact that the Universal Verification Methodology (UVM) has a class library that can be considered bloated. Python was suggested as an alternative to SystemVerilog, which is currently the main Hardware Verification language (HVL), used for building modern testbenches. Firstly, Cocotb was introduced almost ten years ago, then Pyuvm under two years ago. Python verification initiatives promise it is easier to learn( than traditional SystemVerilog), faster, and more productive to write. In this paper we explore the process of writing Python-based testbench, through writing DDR3 SDRAM Controller testbench. The testbench is implemented using the Pyuvm methodology running on top of Cocotb that’s used to interact with the Design under test (DUT). The motivation of this paper is to explore the capabilities of Python based verification, and how much of similarity or difference it does bear compared to traditional SystemVerilog and UVM.

Introducing Y2O3 passivation layer for utilizing TiSiN electrode on ZrO2-based metal-insulator-metal capacitor applications

This study investigates the degradation and improvement of the dielectric properties of ZrO2-based metal-insulator-metal (MIM) capacitors using TiSiN electrodes. As dynamic random-access memory (DRAM) design rules scale down, the mechanical properties of TiSiN electrodes provide advantages over conventional TiN, but also introduce challenges due to Si diffusion into ZrO2 films, forming low-dielectric constant (k) Zr-silicate and defect-related dielectric degradation. We evaluate the dielectric properties of ZrO2 films on TiSiN electrodes and identify significant reductions in the dielectric constant and an increase in DC and AC non-linearity due to Zr-silicate formation. To mitigate these problems, a Y2O3 passivation layer is introduced between the TiSiN electrode and ZrO2 dielectric film. Physical and chemical analyses, including X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS), confirm that Y2O3 passivation effectively suppresses Si diffusion, preventing formation of Zr silicate, and preserving the high-k tetragonal phase of ZrO2. Electrical measurements show that the Y2O3 layer significantly improves the dielectric constant and reduces non-linearity effects. Notably, even at a reduced ZrO2 thickness of 4 nm, a relatively high k value is maintained with Y2O3 passivation. This study concludes that the Y2O3 passivation layer is indispensable for maintaining high dielectric performance in ZrO2-based MIM capacitors with TiSiN electrodes, ensuring stability and efficiency in advanced DRAM applications.

Interfacial layer suppression in ZrO2/TiN stack structured capacitors via atomic layer deposition

Controlling the formation of interfacial layers in dynamic random-access memory (DRAM) capacitors is crucial because it affects electrical performance, such as increasing the equivalent oxide thickness. This study investigates the formation of an interfacial layer during atomic layer deposition (ALD) of ZrO2 on TiN electrodes and examines its influence on electrical properties. Utilizing O3 and H2O as oxygen sources, we quantitatively identified notable differences in the formation of the interfacial TiOx layer. Using O3 results in a thicker TiOx layer with fewer impurities, which lowers the leakage current, whereas H2O creates a thinner interfacial layer with higher impurity levels, leading to an increased leakage current. To optimize these effects, we developed a two-step ALD process that combines both oxygen sources, reducing the interfacial layer thickness while maintaining low leakage currents. This approach significantly improved the electrical performance of capacitors. Furthermore, similar results were observed for HfO2/TiN systems, suggesting that our findings are broadly applicable to high-k dielectric materials.

FMEA-TSTM-NNGA: A Novel Optimization Framework Integrating Failure Mode and Effect Analysis, the Taguchi Method, a Neural Network, and a Genetic Algorithm for Improving the Resistance in Dynamic Random Access Memory Components

Dynamic random access memory (DRAM) serves as a critical component in medical equipment. Given the exacting standards demanded by medical equipment products, manufacturers face pressure to improve their product quality. The electrical characteristics of these products are based on the resistance value of the DRAM components. Hence, the purpose of this study is to optimize the resistance value of DRAM components in medical equipment. We proposed a novel FMEA-TSTM-NNGA framework that integrates failure mode and effect analysis (FMEA), the two-stage Taguchi method (TSTM), neural networks (NN), and genetic algorithms (GA) to optimize the manufacturing process. Moreover, the proposed FMEA-TSTM-NNGA framework achieved a substantial reduction in experimental trials, cutting the required number by a factor of 85.3 when compared to the grid search method. Our framework successfully identified optimal manufacturing condition settings for the resistance values of DRAM components: Depo time = 27 s, Depo O2 flow = 151 sccm, ARC-LTO etch time = 43 s, ARC-LTO etch pressure = 97 mTorr, Ox-SiCO etch time = 91 s, Ox-SiCO gas ratio = 22%, and Polish time = 84 s. The results helped the case company improve the resistance value of DRAM components from 191.1 × 10−3 Ohm to 176.84 × 10−3 Ohm, which is closer to the target value of 176.5 × 10−3 Ohm. The proposed FMEA-TSTM-NNGA framework is designed to operate efficiently on resource-constrained, facilitating real-time adjustments to production attributes. This capability enables DRAM manufacturers to swiftly optimize product quality.

Analysis of hot carrier instability in a floating body cell

Hot carrier instability (HCI) in a floating body cell (FBC) has been investigated. The FBC is a dynamic random-access memory (DRAM) made entirely of a silicon-on-insulator (SOI)-MOS without a capacitor. For FBC realization, there is an influence of a physical phenomenon different from the normal MOS because of its structural and operational characteristics of SOI-MOS. The difference between bulk and SOI-MOS is not yet clear, especially for HCI. In this study, we clarified the importance of the structural and geometrical factors of the FBC cell transistor and the SOI-specific floating body effect in the HCI regime of FBCs.

Low Contact Resistance via Quantum Well Structure in Amorphous InMoO Thin Film Transistors

The amorphous oxide semiconductor (AOS) thin film transistor (TFT) shows promise for use in advanced integrated circuits, such as 2T0C dynamic random-access memory, due to its excellent electronic performance and ability to be fabricated at low temperatures. Nevertheless, the high contact resistance between the metal and AOS restricts the applicability of AOS-TFT. This study demonstrates the achievement of a reduced contact resistance in InMoO (IMO) transistors by using a MoOx interlayer during fabrication. Increasing the oxygen concentration alters the band structure of MoOx and creates a graded Mo-MoOx-IMO structure with a pronounced quantum well at the interlayer between the metal and channel. Consequently, the quantum well’s ability to attract electrons and shape the band edge suppresses the Fermi-level pinning effect, ultimately leading to the establishment of an ohmic contact. The optimized MoOx interlayer showed a significant improvement in contact resistance (∼400%) through the adjustment of oxygen content during annealing procedures. This finding suggests that it is an attractive approach to provide excellent source/drain contacts in future ultra-scaled amorphous oxide semiconductor thin-films.

Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems

DRAM memory controller plays a critical role in maximizing the performance of High Bandwidth Memory by efficiently managing data transfers between the CPU and the memory modules. Thus, they are suitable for low-power data-intensive applications. However, the complexity of DRAM command scheduling combined with tag management overheads in the cache makes the design of in-package cache controllers significantly challenging. Traditional memory controllers often face challenges with static, inflexible access scheduling designed for general applications, leading to suboptimal performance in dynamic environments. On the other hand, while some advanced controllers employing reinforcement learning offer adaptability to workload fluctuations, they tend to introduce hardware complexity and incur longer training latencies. Our approach aims to design low-power and efficient DRAM cache controllers using a machine learning model that dynamically adjusts to workload changes with optimized hardware efficiency and reduced training time. Therefore, we propose a machine learning approach to design low-power and efficient DRAM cache controllers that will leverage the trained model to produce optimal cache command schedules at runtime. The model considers several conditions for each request queue, and chooses the best response among the options. The simulation results show the superiority of our proposed design over the previous algorithms in a set of twelve data-intensive applications; our model is able to improve the performance up to 40% in some cases, and an average of 15% in performance and 10% in power consumption.

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

650 ps SET speed in Ge2Sb2Te5 phase change memory induced by TiO2 dielectric crystal plane

AbstractCrystallization speed of phase change material is one of the main obstacles for the application of phase change memory (PCM) as storage class memory in computing systems, which requires the combination of nonvolatility with ultra‐fast operation speed in nanoseconds. Here, we propose a novel approach to speed up crystallization process of the only commercial phase change chalcogenide Ge2Sb2Te5 (GST). By employing TiO2 as the dielectric layer in phase change device, operation speed of 650 ps has been achieved, which is the fastest among existing representative PCM, and is comparable to the programing speed of commercial dynamic random access memory (DRAM). Because of its octahedral atomic configuration, TiO2 can provide nucleation interfaces for GST, thus facilitating the crystal growth at the determinate interface area. Ti–O–Ti–O four‐fold rings on the (110) plane of tetragonal TiO2 is critical for the fast‐atomic rearrangement in the amorphous matrix of GST that enables ultra‐fast operation speed. The significant improvement of operation speed in PCM through incorporating standard dielectric material TiO2 in DRAM paves the way for the application of phase change memory in high performance cache‐type data storage.image

Implementation of sub-100 nm vertical channel-all-around (CAA) thin-film transistor using thermal atomic layer deposited IGZO channel

In–Ga–Zn–O (IGZO) channel based thin-film transistors (TFT), which exhibit high on–off current ratio and relatively high mobility, has been widely researched due to its back end of line (BEOL)-compatible potential for the next generation dynamic random access memory (DRAM) application. In this work, thermal atomic layer deposition (TALD) indium gallium zinc oxide (IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition (ALD) process. In addition, thin-film transistors (TFTs) with vertical channel-all-around (CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.