Dynamic Power Optimization Research Articles

Power Optimization in a Non-Coordinated Secondary Infrastructure in a Heterogeneous Cognitive Radio Network

In this paper we describe a novel approach that combines dynamic spectrum allocation and transmission power optimization for the secondary network users in an heterogeneous cognitive radio network. The proposed approach builds upon reinforcement learning and convex optimization procedures. Furthermore, the several key components, i.e. inter-cell interference, path loss, and fading have been considered when designing the power optimization algorithm. Simulation results show that the proposed approach improves the QoS of the system by up to 10 dB in terms of SINR and by up to 4% in terms of spectral efficiency while maintaining the average dissatisfaction probability close to that of the non-optimized approach.DOI: http://dx.doi.org/10.5755/j01.eee.21.3.10526

(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS

As CMOS technology scales down, two paths are pursued by the industry to overcome the fundamental limits of traditional planar bulk transistors. One is the introduction of a Tri-Gate or FinFET transistor at the 22 and 16 nm nodes [1, 2]. These architectures provide impressive drive currents per footprint at low supply voltages because of the 3-D conduction channel and excellent electrostatic control. Conversely, they have high gate and parasitic capacitances, proportional to the 3-D effective W increase, which negatively impacts both the speed and active power consumption. Alternatively FDSOI provides an evolutionary path. First introduced at the 28nm node [3], FDSOI includes excellent mismatch properties, a simplified planar manufacturing process vs 3-D finFET technology and capitalization of existing design techniques. It also extends the possibility of back biasing and therefore offers unique “smart” solutions for dynamic power optimization [4]. The technology presented in this paper furthers the appeal of FDSOI to the 14nm node [5]. Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain [5]. Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built [6]. The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges [7] (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated. After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node. As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in [5] a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd. These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications.

A dynamically reconfigurable architecture system for time-varying image constraints (DRASTIC) for motion JPEG

We propose a dynamically reconfigurable system for time-varying image constraints (DRASTIC) for applications in video communications. DRASTIC defines a framework for both joint and independent optimization of dynamic power, image quality, and bitrate subject to different constraint scenarios. We demonstrate DRASTIC for intra-mode video encoding for MJPEG. However, since the DCT is critical component of most video coding standards, our approach can be extended to modern standards such as AVC (H.264), and emerging standards such as HEVC (H.265), and VP9. Based on a hardware–software co-design approach, we define a family of scalable 2D DCT hardware modules that are jointly optimized with the quality factor (in software). We generate a total of 1,280 configurations of which 841 were found to be Pareto optimal. For full 2D DCT calculation, the results indicate that the proposed method is DRASTIC mode implementation at least as good or significantly better than any previously published implementation. A scalable, real-time controller is used for selecting an appropriate configuration so as to meet time-varying constraints. The real-time controller is shown to satisfy the constraints of different communications modes (e.g., minimum dynamic power, maximum image quality, etc.) as well as to adapt to mode changes. Empirically, we have found that the DRASTIC controller adapts to meet the new constraints within five video frames of a mode change. Overall, the proposed approach yields significant savings over the use of comparable static architectures.

Distributed Targets Tracking with Dynamic Power Optimization for Wireless Sensor Networks

Distributed Targets Tracking with Dynamic Power Optimization for Wireless Sensor Networks

A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization

In this paper, we propose a novel gate sizing approach for circuit optimization in the presence of scarce information about the distributions of the process variations. The proposed methodology relies upon the concepts of utility theory and risk minimization for multimetric optimization of delay, dynamic power, leakage power, and crosstalk noise, via gate sizing. A deterministic linear equivalent model from a fundamentally stochastic design optimization problem, ensuring high levels of expected utility and significant speedup in the optimization process for large circuits is derived in this work. Experimental results indicate that the proposed algorithm is efficient in terms of optimization results with multifold speedup in execution times compared to the traditional approaches.

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.

An Interconnect Bus Power Optimization Method

A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.03% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses.

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high- k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high- k 45 nm.

Energy–Performance Tunable Logic

We propose a new logic family that enables the user to tune the transistor's effective threshold voltage after fabrication for higher speed or lower power. This technique along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the application/workload requirements. Programmable interconnect from an FPGA was implemented using this logic family on a 90 nm CMOS test chip. Measurements show that this topology provides twice the tuning range in the energy-performance space compared to a conventional interconnect utilizing only supply voltage scaling. For most of the performance range, this circuit consumes 35% less energy compared to a state-of-the-art design. The circuit is an externally static, internally pulse-mode topology which can replace static circuits without requiring significant changes to the system.

Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems

Reconfigurable architectures are increasingly often applied in various industrial data processing applications, due to the possibility for performing parallel computations and achieving a simplified Systemon-Chip design flow. Furthermore, the exploitation of dynamic and partial hardware reconfiguration has been investigated in different research projects, often in systems based on Xilinx Virtex 2/4 FPGA families, by time-multiplexing hardware resources for multiple functions. This paper describes the exploitation of partial reconfiguration for dynamic power management in a low-power Spartan 3-based level measurement application. The reconfiguration process is thereby applied to optimize system implementation according to the applications requirements on power consumption and performance.

Dynamic power optimization with target prediction for measurement in wireless sensor networks

Energy constraint is a critical problem for practical applications in wireless sensor networks.Focused on the energy efficiency problem of wireless sensor networks,a dynamic power optimization method is proposed with target prediction. Particle filter is introduced to predict target state,which is adopted to awaken wireless sensor nodes so that their sleep time is prolonged.With the distributed computing capability of nodes,distributed genetic algorithm and simulated anneal is proposed to optimize the energy consumption of measurement. Considering the application of target tracking,target position prediction,node sleep scheduling and optimal sensing node selection are implemented.Moreover,a routing scheme of for- warding nodes is presented to achieve extra energy conserva- tion.Experimental results of target tracking verified that en- ergy-efficiency is enhanced by dynamic power optimization with target prediction in wireless sensor networks.

Dynamic Power Optimization Targeting User Delays in Interactive Systems

Power has become a major concern for mobile computing systems such as laptops and handhelds, on which a significant fraction of software usage is interactive instead of compute-intensive. For interactive systems, an analysis shows that more than 90 percent of system energy and time is spent waiting for user input. Such idle periods provide vast opportunities for dynamic power management (DPM) and voltage scaling (DVS) techniques to reduce system energy. In this work, we propose to utilize user interface information to predict user delays based on human-computer interaction history and theories from the field of psychology. We show that such a delay prediction can be combined with DPM/DVS for aggressive power optimization. We verify the effectiveness of our methodologies with usage traces collected on a personal digital assistant (PDA) and a system power model based on accurate measurements. Experiments show that using predicted user delays for DPM/DVS achieves an average of 21.9 percent system energy reduction with little sacrifice in user productivity or satisfaction

Dynamic Power Optimization of Active Filters With Application to Zero-IF Receivers

This paper describes the use of dynamic impedance scaling and dynamic biasing to dynamically optimize the power dissipation of filters depending on the inband signal level. Transients due to the dynamical changes inside the filter are prevented thanks to the implementation of appropriate switching algorithms. To illustrate the concept, a fifth-order Chebychev low-pass active-RC filter with 100-kHz cutoff frequency, designed for partial channel selection in a zero-IF GSM receiver, is presented. The filter is fabricated in a standard 0.18-/spl mu/m CMOS process and uses a 1.2-V power supply. It consumes 2.22-mA supply current during the presence of the minimum receivable signal. The power dissipation decreases by a factor of 2 as the desired signal strength increases by 3 dB, until it reaches its minimum possible value of 0.46 mW. There are a total of five power settings in the filter.

STOCHASTIC POWER CONTROL FOR WIRELESS SYSTEMS: CENTRALIZED DYNAMIC SOLUTIONS AND ASPECTS OF DECENTRALIZED CONTROL

This paper considers power control for log-normal fading channels. A rate based power set point control model and associated performance measures are introduced. The value function of the stochastic optimal control is a viscosity solution to the associated HJB equation and is approximated by smooth functions. Finally, by introducing multi-objective indices, we give a game theoretic formulation to the dynamic power optimization problem.