Dynamic Noise Margin Research Articles

A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI

This work proposes an static random access memory (SRAM) with column-based split cell-VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28-nm FDSOI technology. The proposed CS-CVSS and DAWA techniques improve both half-selected (HS) static noise margin (SNM) and write margin. They also improve HS dynamic noise margin (HS-DNM) by leveraging write through virtual ground with reduced load in the proposed write port. The proposed 3T read port enhances sensing margin by minimizing read bitline leakage through negative gate-to-source voltage regardless of cell data. A 16-kb 9T SRAM test chip demonstrated the minimum operating voltage for write and read operations as 0.47 and 0.25 V, respectively. The minimum energy of 6.72 pJ is achieved at 0.5 V.

Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System

In this paper, an ultra-low power (ULP) 8T static random access memory (SRAM) is proposed. The proposed SRAM shows better results as compared with conventional SRAMs in terms of leakage power, write static noise margin, write-ability, read margin, and $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ . It is observed that the leakage power is reduced to $82\times $ (times) and $75\times $ as compared with the conventional 6T SRAM and read decoupled (RD)-8T SRAM, respectively, at 300 mV VDD. In addition, write static noise margin (WSNM), write trip point (WTP), read dynamic noise margin, and $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio are also improved by 7.1%, 43%, 7.4%, and $74\times $ than conventional 6T SRAM, respectively, at 0.3 V VDD. Moreover, the WSNM, WTP, and $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ values are improved by 6.67%, 7.14%, and $68\times $ as compared with RD-8T SRAM, respectively, at 0.3 V VDD. Furthermore, a fast, reliable, less memory usage object tracking algorithm and implementation of its memory block using ULP 8T SRAM are proposed. A quadtree-based approach is employed to diminish the bounding box and to reduce the computations for fast and low power object tracking. This, in turn, minimizes the complexity of the algorithm and reduces the memory requirement for tracking. The proposed object detection and tracking method are based on macroblock resizing, which demonstrates an accuracy rate of 96.5%. In addition, the average total power consumption for object detection and tracking which includes writing, read and hold power is $1.63\times $ and $1.45\times $ lesser than C6T and RD8T SRAM at 0.3 V VDD.

A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS

Near-threshold operation is garnering growing attention for ultra-low power applications despite the fact the reliability of the near-threshold digital systems warrants unprecedented scrutiny of robustness measures to ensure correct functionality under stringent environmental and manufacturing scattering specifications. In this paper, an ideal theoretical read and write static noise margins (RSNM/WSNM) are discussed. In addition, a 12T SRAM bit cell is proposed in order to reach the theoretical WSNM limit. This could be achieved by eliminating a feedback of back-to-back inverters by means of data-dependent supply cutoff during write operation. This allows the proposed bit cell to enlarge write margin dramatically. Many previous works also attempt to cutoff the supply, but many of them were not data dependent. Monte-Carlo (MC) simulation results show the proposed 12T SRAM bit cell is more robust in static and dynamic noise margin than the conventional 6T and 8T SRAM bit cells as well as a 10T bit cell. The area overhead of the proposed bit cell is 1.96 times and 1.74 times greater than the 6T and 8T bit cells, respectively. Analytical models of WSNM for the 12T bit cell in the super-threshold region and the sub-threshold region are also proposed.

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage

A single-bit-line (BL) static RAM (SRAM) circuit that employs adiabatic charging of a word line during a read operation was found to provide a large dynamic noise margin (DNM) for reading. Single-BL reading is achieved by using a left access transistor and a shared reading port. The shared reading port greatly reduces the BL capacitance, enabling the voltage of the BL connected to the low-voltage node of the flip-flop to change from the precharge voltage to GND. An analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit. This circuit enables the design of an SRAM that is smaller than a conventional one, resulting in lower energy consumption.

Sram cell stability metric under transient voltage noise

The conventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mismatch variations, bulk static noise, supply ring offset, quasi static temperature changes are well characterized by means of the Static Noise Margin (SNM). However, a significant number of disturbance sources present a transient behavior, which is ignored by the static analysis, but has to be taken into consideration for a complete characterization of the cell's behavior. In this paper, a metric to evaluate the SRAM cell's robustness in the presence of transient voltage noise is proposed. The metric is obtained by evaluating the energies of the noise signals able to flip the SRAM cell's state. In this work, the Dynamic Noise Margin (DNM) metric is defined as the minimum signal energy of the voltage noise able to flip the cell's state in data retention mode. The purpose of the proposed metric is to compare different cell designs in terms of robustness to assess the design parameters which will yield the most stable cell in front of static and dynamic disturbances.

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65nm technology models are used for simulations.

A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100 nm technology. In this paper, we present a highly stable 2-port 8T SRAM cell for high speed application in 65 nm technology. The proposed design provides high stability under simultaneous read/write disturbed access without reducing the I cell . The cell characteristic is extensively examined under random variation. The dynamic read noise margin is improved by 95% over conventional dual port SRAM. The zero-precharge sensing and virtual ground scheme reduce read path leakage current by 95% over conventional high precharge 2-port SRAM cell. The cell current is improved by 52% over conventional design. Finally, an 8 Kb bit-interleaved 2-stage pipelined SRAM architecture is presented using proposed cell. The 2-stage pipeline architecture provides data transfer bandwidth of 3.1 GB/s. Area-efficient 2-stage decoder layout helps to avoid pseudo read problem in unselected cells without sacrificing memory access time.

Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation

This paper presents the analysis of dynamic noise margin of proposed 8T static random access memory (SRAM) cell. The proposed SRAM cell has two voltage sources, one connected to the bit line and the other is connected to bitbar line. These voltage sources are used to reduce the swing voltage at the output nodes. This reduction of swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell during switching activity. The dynamic noise margin (DNM) analysis is carried out and the results are compared with those of conventional 6T SRAM cell and existing 10T SRAM cell for different word line pulse widths. The proposed SRAM cell has higher value of DNM which ensures the higher stability than 6T and 10T SRAM cells. Simulation has been done in 65nm environment with a power supply of 1V. Microwind 3.1 is used for simulation purpose. 

Quantifying Dynamic Stability of Genetic Memory Circuits

Bistability/Multistability has been found in many biological systems including genetic memory circuits. Proper characterization of system stability helps to understand biological functions and has potential applications in fields such as synthetic biology. Existing methods of analyzing bistability are either qualitative or in a static way. Assuming the circuit is in a steady state, the latter can only reveal the susceptibility of the stability to injected DC noises. However, this can be inappropriate and inadequate as dynamics are crucial for many biological networks. In this paper, we quantitatively characterize the dynamic stability of a genetic conditional memory circuit by developing new dynamic noise margin (DNM) concepts and associated algorithms based on system theory. Taking into account the duration of the noisy perturbation, the DNMs are more general cases of their static counterparts. Using our techniques, we analyze the noise immunity of the memory circuit and derive insights on dynamic hold and write operations. Considering cell-to-cell variations, our parametric analysis reveals that the dynamic stability of the memory circuit has significantly varying sensitivities to underlying biochemical reactions attributable to differences in structure, time scales, and nonlinear interactions between reactions. With proper extensions, our techniques are broadly applicable to other multistable biological systems.

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in I_ON is not sufficient to improve the circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal-oxide-semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of I_ON, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same off-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts.

Teaching Digital Noise and Noise Margin Issues in Engineering Education

This work presents digital noise in signal integrity and clarifies noise margin issues in digital electronics education. For the static noise margin, the traditional definition violates the basic principle of noise. The embedded rectangle method to define the static noise margin is a more reliable criterion. For the dynamic noise margin (DNM), several approaches have been evaluated. The best way to teach the student DNM is suggested.

Dynamic noise model and its application to high speed circuit design

A dynamic noise model is developed and applied to analyze the noise immunities of precharge-evaluate circuits. With cross-talk being the main source of noise injection in the circuit, a simple metric represented as voltage–time product can be used to quantify the dynamic noise-margin. This is verified through HSPICE simulation on DOMINO gates. Based on this dynamic noise model, a tool is developed and applied to find the static and dynamic noise-margins at various points in the circuit with the effects of charge share and power/ground bounce taken into account. Obtained noise-margins are translated into maximum allowable coupling capacitances between the nodes for different types of precharge-evaluate logic circuits. The results show the difference in dynamic noise immunities in different logic families. Accurate estimates of dynamic noise-margins and coupling capacitance bounds will help design robust CMOS circuits.

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.