Sram cell stability metric under transient voltage noise

Abstract

The conventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mismatch variations, bulk static noise, supply ring offset, quasi static temperature changes are well characterized by means of the Static Noise Margin (SNM). However, a significant number of disturbance sources present a transient behavior, which is ignored by the static analysis, but has to be taken into consideration for a complete characterization of the cell's behavior. In this paper, a metric to evaluate the SRAM cell's robustness in the presence of transient voltage noise is proposed. The metric is obtained by evaluating the energies of the noise signals able to flip the SRAM cell's state. In this work, the Dynamic Noise Margin (DNM) metric is defined as the minimum signal energy of the voltage noise able to flip the cell's state in data retention mode. The purpose of the proposed metric is to compare different cell designs in terms of robustness to assess the design parameters which will yield the most stable cell in front of static and dynamic disturbances.