Dynamic Element Matching Research Articles

A 0.075 mm2 BJT-based temperature sensor with a one-point trimmed 3[formula omitted] inaccuracy of ±0.97 °C from −40 °C to 120 °C

This paper presents a bipolar junction transistor (BJT)-based CMOS temperature sensor for high accuracy, small-scale area, and low power consumption. A structure with a feedback amplifier biasing NPN transistors, combined with dynamic element matching (DEM), is proposed to avoid the effects of errors arising from the limited current gain of substrate PNP transistors in deep-submicron processes. Moreover, the switched capacitor (SC) integrators employ two single-stage cascode amplifiers for alternating cyclic sampling and integration, effectively simplifying the circuit design and reducing the operating voltage. The proposed sensor is fabricated with a standard 180 nm CMOS process, occupying an active chip area of 0.075 mm2. It consumes 39.1 μW of power at room temperature, operating with a supply voltage of 1.8 V. The measurements indicate that the sensor exhibits an inaccuracy of ±0.97 °C (3σ) across the temperature range from −40 °C to 120 °C following a single-point temperature calibration.

A ±0.15 °C (3σ) Inaccuracy CMOS Smart Temperature Sensor from −40 °C to 125 °C with a 10 ms Conversion Time-Leveraging an Adaptative Decimation Filter in 65 nm CMOS Technology

This paper presents the design and implementation of a highly accurate smart temperature sensor designed in 65 nm CMOS technology. The sensor exhibits a ±0.15 °C (3σ) error across a wide temperature range from −40 °C to 125 °C, catering to diverse application needs. Leveraging advanced CMOS technology, the sensor employs an adaptive decimation filter that allows us to control the conversion time, ensuring that the accuracy of the conversion is maintained even in challenging conditions. The proposed sensor architecture integrates advanced techniques for temperature sensing for improved accuracy and reliability. Through meticulous circuit design and the usage of dynamic element matching, chopping, and calibration/trimming, the sensor demonstrates exceptional performance characteristics, making it suitable for various industrial, automotive, and consumer electronics applications demanding high precision temperature monitoring.

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

A Shifting Current Mirror Driver Circuit for Electrical Impedance Tomography Applications

This brief describes a high power efficiency, high linearity current driver for wearable electrical impedance tomography (EIT). It is extremely important to improve the power efficiency of the current driver circuit for wearable EIT applications because it consumes the majority of the power. As such, we propose a multi-stage shifting current mirror (SCM) current-steering current driver circuit with customized dynamic element matching (DEM) techniques to suppress harmonic distortion (HD) to the greatest extent. Furthermore, the placement of switches in the current mirror circuit is optimized to reduce glitches during the switching phases. Operating between 14 MHz to 56 MHz, the power consumptions for the current mirror and the digital control logic are 21.6-141.6 lW and 64.8-438 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.3 μW/kHz while maintaining a total harmonic distortion (HD) of <-43 dB (0.7%).

A 13-Level SC DAC Achieving High Linearity With a Simple DEM for Wideband CT DSMs

Wideband continuous-time (CT) Delta-Sigma modulators (DSMs) generally demand multi-level digital-to-analog converters (DACs), which require a linearization technique to overcome the problem of component mismatches. Dynamic element matching (DEM) is a popular DAC linearization approach but can be challenging to implement in a wideband DSM, particularly when there are many DAC elements. In this manuscript, we introduce a 13-level switched-capacitor (SC) DAC achieving high linearity with a simple DEM that rotates three unit elements only and does not incur excess loop delay. In a traditional CT DSM, a DAC of the SC type increases the amplifier settling requirements and damages the alias rejection. Earlier works have shown that these problems can be solved if the CT DSM adopts a passive RC frontend. A 10-MHz bandwidth CT DSM is designed in the 65-nm CMOS technology to validate the proposed DAC. Simulations show that the DAC enables a spurious-free dynamic range greater than 87.7 dB and a signal-to-noise pulse distortion ratio greater than 80.5 dB under a 1% capacitor mismatch, a 2% reference voltage error, and process variations.

A 4.21-μV Offset Voltage and 42-nV/√Hz Input Noise Chopper Operational Amplifier with Dynamic Element Matching

This paper presents a high-efficiency operational amplifier (op-amp) used in the readout circuit of micro-sensor. The chopping and dynamic element matching (DEM) techniques are used in the proposed design, which greatly reduce the offset voltage and flicker noise [Formula: see text] noise) of the op-amp. By optimizing the circuit structure, the maximum chopping frequency is increased to 2[Formula: see text]MHz when the offset voltage is less than [Formula: see text][Formula: see text]V. Therefore, the maximum bandwidth of signal processing can be up to 1MHz. The proposed circuit is designed and fabricated using TSMC 0.18-[Formula: see text]m 1P5M CMOS technology. It occupies an area of 0.16[Formula: see text]mm2 and consumes [Formula: see text]A from a 1.8-V supply. When the chopping frequency is 100[Formula: see text]kHz, the input-referred offset voltage is 4.21[Formula: see text][Formula: see text]V and the input-referred noise is 42[Formula: see text]nV[Formula: see text]Hz. It achieves a noise efficiency factor of 7.82 and a power efficiency factor of 110.07.

A glitch energy reduction method with low complexity dynamic element matching for data converters

Due to the appearance of huge glitch while using traditional Dynamic Element Matching (DEM) in data converters, different kinds of glitch-reduce structures are designed into DEM. However, most of these structures will work with high complexity. Based on random-rotation-binary-weighted selection (RRBS), this paper presents a novel low complexity glitch-reduced DEM algorithm, which can greatly reduce mismatch. The proposed DEM constructs glitch-reduce structure through data selector and comparator, so the complexity is reduced through using less components. As a result, the glitch-reduced DEM increases spurious free dynamic range (SFDR) to 92.47dB at 7.6MHz. Moreover, compared with conventional RRBS, glitch-reduced DEM makes the glitch reduce by 49% with low complexity in a 12-bit digital-to-analog converter (DAC).

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

An ultra-low power dissipation CMOS temperature sensor with an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C

An ultra-low power, high accuracy BJT-based CMOS temperature sensor is presented in this paper. The temperature sensor consists of analog front end (AFE) and hybrid ADC. In AFE design, two dynamic element matching (DEM) control modules are applied to current mirrors and bipolar transistors reduce the mismatch greatly and enhance the sensitivity of the temperature sensor. A hybrid ADC that combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce the power dissipation. The proposed sensor is fabricated in a 0.18 μm CMOS process, occupying an area of 0.14 mm2. The measured results indicate that, the total current is 6.5 μA from a 1.8 V power supply, and achieves an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C.

A low-noise and mismatch-tolerant current-mirror-based potentiostat circuit for glucose monitoring

Potentiostat circuits are widely used to monitor biochemical signals such as glucose and viruses. Here, we proposed a potentiostat circuit that is an amperometric sensor with a three-electrode configuration. Low-noise and mismatch-tolerant characteristics are essential for the accurate measurement of biochemical signals. To achieve low-noise characteristics, we apply the chopper stabilization technique to a trans-impedance amplifier (TIA) and a control amplifier (CA). In addition, dynamic element matching (DEM) was adopted for the current mirror to achieve mismatch-tolerance. The proposed potentiostat consists of a CA, current mirror, and TIA. CA maintains the voltage between the working electrode (WE) and counter electrode (CE). The current mirror transmits a low-noise and mismatch-tolerant current signal to the TIA. The TIA converts the minute current signal into an amplified voltage signal. The proposed circuit was fabricated using a TSMC 180 nm CMOS process. The input-referred noise is 857 fA/√Hz at 1 Hz. The power consumption is 273.9 μW with a 1.8 V power supply.

A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

An Energy-Efficient BJT-Based Temperature Sensor with ±0.8 °C (3σ) Inaccuracy from −50 to 150 °C

This article presents an energy-efficient BJT-based temperature sensor. The output of sensing front-ends is modulated by employing an incremental Δ-Σ ADC as a readout interface. The cascoded floating-inverter-based dynamic amplifier (FIA) is used as the integrator instead of the conventional operational transconductance amplifier (OTA) to achieve a low power consumption. To enhance the accuracy, chopping and dynamic element matching (DEM) are applied to eliminate the component mismatch error while β-compensation resistor and optimized bias current are used to minimize the effect of β variation. Fabricated in a standard 180-nm CMOS process, this sensor has an active area of 0.13 mm2. While dissipating only 45.7 μW in total, the sensor achieves an inaccuracy of ±0.8 °C (3σ) from -50 °C to 150 °C after one-point calibration.

A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR

This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> HV-CMOS technology in a 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times32$ </tex-math></inline-formula> array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.

High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique

This brief presents a current-steering digital-to-analog converter (DAC) with “4-bit splitting +8-bit binary” segmented topology. The proposed splitting decoding method can optimize the differential nonlinearity and output glitches of the DAC with a more simplified circuit scale than unary decoding. With a data-transmission topology, the splitting decoder has a low latency and accommodates fast synchronization control of current source switches. Moreover, the dynamic element matching (DEM) technique is used to suppress the harmonic distortion caused by the splitting current source mismatch. The DAC is designed using 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an area of 452.82 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times491.76\,\,\mu \text{m}$ </tex-math></inline-formula> . With a 1.8 V analog supply and a 1.2 V digital supply, the DAC dissipates 12.2 mW at 500 MS/s. The spurious-free dynamic range of the DAC improves from 63.18 dB to 73.30 dB using DEM technique for an output signal of 8.30 MHz and by 8-10 dB within the Nyquist bandwidth.

A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.2-11.7$ </tex-math></inline-formula> bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2.

A novel capacitor recombination calibration method applied to 18-bit SAR ADC

In this paper, a calibration method applied to Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is designed, especially applied to the capacitive array in resistive–capacitive combined SAR ADC. Conventionally, auxiliary Digital-to-Analog Converter (DAC) foreground calibration, dynamic element matching (DEM) or digital background calibration are widely used to enhance linearity of data converters. This paper proposes an off-line capacitor selection calibration method that uses an optimal sequence of unity elements for an overall improvement of Signal to Noise and Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), differential nonlinearity (DNL) and integral nonlinearity (INL). It is worth mentioning that the capacitor mismatch only needs to be calibrated after power on, this kind of foreground calibration will not increase the power consumption of ADC during the normal operation, while the background calibration will consume power consumption all the time. It is important that the calibration proposed is highly relied on a high resolution comparator. This paper provides a high resolution comparator design, the resolution of the comparator reaches 8.35 μV, which already satisfies the demand of a 18-bit differential SAR ADC. During the process of calibration, all capacitors are divided into unit capacitors, and then the capacitors are sorted, reorganized to form each bit. The calibration method is verified by simulating a 18-bit SAR ADC with 500 Monte-Carlo runs, the simulation results show that the average value of SFDR is enhanced by about 36 dB and the average value of SNDR is enhanced by about 27 dB. Therefore, the proposed method is simple and significantly improves the static and dynamic performance of the ADC without obvious additional hardware, and greatly saves area and power consumption. Finally, it is worth mentioning that in high-precision SAR ADCs design, especially above 16 bits, comparator noise and the voltage coefficient of capacitors are the main factors limiting ADC performance, which are not considered in this work.

A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters

Mismatch-based nonlinear distortion greatly influences the accuracy and spurious-free dynamic range (SFDR) of current steering digital-to-analog converters (CS-DACs). Dynamic element matching (DEM) is an intelligent technique that reduces both amplitude and timing mismatch errors. In conventional DEM DACs, further enhancement of SFDR at higher frequencies is constrained due to the presence of intersegment mismatch errors in separate segmented structures. In this article, a pairwise swap enabled randomized DEM (PSER-DEM) technique is proposed to address the intersegment mismatch effect in segmented CS-DAC. This technique uses both randomization and swapping between row and column elements of current source cells for selecting the unit current source elements. A 6-bit CS-DAC with the PSER-DEM technique has been implemented with the UMC 180-nm 1.8-V CMOS process. The proposed DAC architectures with circuit description and measurement results are demonstrated briefly. A 48.15-dB SFDR with more than 6-dB enhancement is achieved from the measurement result. The proposed architecture for 10-bit CS-DAC is presented with vigorous mismatch-based Monte Carlo simulation results, which shows more than 70-dB SFDR for the entire Nyquist range frequency with more than 7-dB improvement from the conventional DEM DACs. Along with the PSER-DEM technique, a signal-dependent randomization concept is proposed to reduce the element transition rate and switching activity of current cells, which reduced the power consumption up to 4 mW for oversampling DACs. A comparative assessment is presented with state-of-the-art literature on DEM DAC structures. The proposed method has exhibited superior performance, which signifies the suitability for high-speed and high-resolution CS-DACs.

Time-domain Continuous-time Delta-sigma Modulator using VCO-based Integrator and GRO-based Quantizer

This paper presents a 3SUPrd/SUP-order time-domain continuous-time delta-sigma modulator (CTDSM) using two voltage-controlled oscillator (VCO)-based integrators and a gated ring oscillator (GRO)-based quantizer. The GRO-based quantizer has 1SUPst/SUP-order noise-shaping characteristics without the increase of the signal transfer function (STF) order and has magnificent linearity. Also, the output of the GRO-based quantizer has an intrinsic data weighted averaging (DWA)-based dynamic element matching (DEM) pattern that is less susceptible to the DAC mismatch. The PWM signal, which is the input of the GRO-based quantizer, is generated by the VCO-based integrator without additional blocks. In the pre-layout simulation, the CTDSM consumes 3.84 mW and achieves an SNDR of 71.2 dB at a 400-MSs sampling frequency and a 10-MHz bandwidth.

High-resolution calibrated successive-approximation-register analog-to-digital converter

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively.