Dynamic Amplifier Research Articles

IMPROVEMENT OF POINT LEPREAU GENERATING STATION ROP DETECTOR CHARACTERISTICS BY ADJUSTING GAINS IN COMPENSATION AMPLIFIERS

Canadian Pressurized Heavy Water Reactors are protected against reactor overpower by 2 independent shutdown systems: Shut Down System 1 and 2. At Point Lepreau Generating Station, these shutdown systems can be actuated by signals from Platinum-clad Inconel In-Core Flux Detectors measuring the neutron flux. These detectors have a complex dynamic behaviour, characterized by “prompt” and “delayed” components with respect to immediate changes in the in-core neutron flux. In aging detectors, it was found that the prompt response decreases. A detector response that actuates the shutdown system effectively has to have a large prompt response and a small delayed response. These required responses may be obtained by adjusting the dynamic compensation amplifiers (compensator) settings. This paper presents the measured results of a compensation adjustment procedure for the in-core platinum-clad Inconel detectors. The compensation is computed from the detector parameters estimated by VS, a fully automated and qualified computer program that analyzes the response of the detectors.

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low V DD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-μm silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control.

Operating Modes of Dynamic Power Supply Transmitter Amplifiers

Any amplifier operated with a varying supply voltage is actually a three-port circuit, having two inputs and one output. When an amplifier is characterized as a three-port for dynamic supply voltage operation, three separate operating modes appear: linear L-mode and the two nonlinear modes C-mode and P-mode. Each of these modes, along with their relationships and differences, are identified, characterized, and discussed. Relations of these modes to the dynamic power supply transmitter techniques of envelope tracking and/or direct polar are presented. Measurements are reported that provide experimental verification for these amplifier operating modes.

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique

This paper proposes an ultra-low-voltage, wide signal swing, and clock-scalable differential dynamic amplifier using a common-mode voltage detection technique. The essential characteristics of an amplifier, such as gain, linearity, power consumption, noise, etc., are analyzed. In measurement, the proposed dynamic amplifier achieves a 13dB gain with less than 1dB drop over a differential output signal swing of 340mVpp with a supply voltage of 0.5V. The attained maximum operating frequency is 700MHz. With a 0.7V supply, the gain increases to 16dB with a signal swing of 700mVpp. The prototype amplifier is fabricated in 90nm CMOS technology with the low threshold voltage and the deep N-well options.

Study on the Influences on Microstructure and Properties of High-Strength Grey Cast Iron in Addition to Alloying Elements Nb

The increase of the strength of gray cast iron is mainly depended on alloying. However, with the improvement of strength, its processing performance will always decrease. So three different gray cast irons are studied in this experiment, including adding 0.1% Nb elements, adding 0.2% Nb elements and adding 0.3% Nb elements, to investigate the Nbs effect to the mechanical performance of gray cast iron, we adopt Dynamic Strain Amplifier to measure cutting force to evaluate processing performance, use Optical Microscope and Electron Microscopy observe each samples organization, explains the relationship between Nbs content and the mechanical and processing performance of gray cast iron from micro-level. Finally, we draw the conclusion: when the Nb comes to 0.3 percent, the appearance of E-type graphite and Nb carbide durum granular will greatly decrease its processing performance.

A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

Performance analysis of dynamic erbium-doped fiber amplifier simulator

A real time multichannel dynamic erbium doped fiber amplifier (EDFA) Simulink model with flat gain and gain clamping facility has been developed on a MATLAB platform. We model the EDFA simulator with one-dimensional nonlinear differential equation that describes the time dependent population density. For the model to show gain flattening multiplexed channels at different wavelengths, the MATLAB function block is used. Next, to simulate the noise performance of EDFA. New forward amplified spontaneous emission (ASE) noise blocks are designed that add noise dynamically at signal wavelength. The model has been implemented in the study of performance characteristics of an EDFA in both C - and L -band signal amplification by simulation. Based on the designed ASE generator, noise figure for different signal wavelengths are calculated. For 980 nm pump power, the noise figure almost reaches the practical limit of 3 dB whereas for 1480 nm pump power, a variation of about 1.5 dB and 0.8 dB is observed from the practical limit for the C - and L -bands, respectively. The present model can be implemented successfully as a test bed in the study of EDFA gain dynamics over the entire third optical communication bandwidth (1525 to 1690 nm) in signal amplification.

A new CST method for Carrier‐type dynamic strain amplifier with C component on four legs of bridge

AbstractCarrier‐type dynamic strain amplifiers are frequently used for stress measurement with strain gages. That is because the carrier‐type dynamic strain amplifier can perform high precision measurement since it is highly resistant to external noise or power noise in the field. The strain gage has little effect on the specimen being measured since it is small and light. However, it is required to connect the input cable from the target strain gage to the amplifier. When using the carrier‐type dynamic amplifier, distributed capacitance due to the input cable greatly affects zero point variation. Changes in the distributed capacitance degrade the stability of the dynamic strain amplifier.We present a new Dual Feedback CST (Capacitance Self Tracing) method that detects, self‐tracks, and eliminates the capacitive component generated in any leg of the measuring bridge. The zero‐point variation is not affected by the carrier frequency and resistance value and can be canceled if the bridge is balanced in the CST method. We conducted experiments with strain gage resistances of 120 and 350 ohms and carrier frequencies of 5, 12, and 28 kHz and verified the zero‐point stability. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(1): 11–18, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22294

Dynamic Bridge Piezoelectric Amplifiers with Signal Generator

Piezoelectric amplifier is a very important part of the piezoelectric actuator. Not only positioning accuracy, but also dynamic performance and power are demanded more and more highly. At present piezoelectric amplifier are mainly used in static applications, power and frequency response are usually incompatible. This paper developed a new type of piezoelectric amplifier to meet high demand for dynamic, which takes dual-power supply, bridge-output to achieved slew rate, power were doubled, and maintain a wide frequency range at the same time. Controller implements DDS unit through FPGA, which could achieve sine, triangle, square and sawtooth.

FPGA-implementation of dynamic time delay neural network for power amplifier behavioral modeling

In this paper, we propose new architectures for FPGA-implementation of a dynamic neural network power amplifier behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx system generator for DSP and the Virtex-6 FPGA ML605 evaluation kit. Different RVTDNN architectures are proposed for various values of the number of hidden neurons, the activation function resolution, and the fixed-point data format. These architectures are evaluated and compared in terms of modeling performances and resource utilization using 16-QAM modulated test signal.

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

AC Read-Out Circuits for Single Pixel Characterization of TES Microcalorimeters and Bolometers

SRON is developing Frequency Domain Multiplexing (FDM) for the read-out of transition edge sensor (TES) soft x-ray microcalorimeters for the XMS instrument of the International X-ray Observatory and far-infrared bolometers for the SAFARI instrument on the Japanese mission SPICA. In FDM the TESs are AC voltage biased at frequencies from 0.5 to 6 MHz in a superconducting LC resonant circuit and the signal is read-out by low noise and high dynamic range SQUIDs amplifiers. The TES works as an amplitude modulator. We report on several AC bias experiments performed on different detectors. In particular, we discuss the results on the characterization of Goddard Space Flight Center x-ray pixels and SRON bolometers. The paper focuses on the analysis of different read-out configurations developed to optimize the noise and the impedance matching between the detectors and the SQUID amplifier. A novel feedback network electronics has been developed to keep the SQUID in flux locked loop, when coupled to superconducting high Q circuits, and to optimally tune the resonant bias circuit. The achieved detector performances are discussed in view of the instrument requirement for the two space missions.

The Realization and Analysis of Capacitance Self Tracing (CST) Method for Wide Band Response Measurement of Carrier Type Dynamic Strain Amplifier

Carrier type dynamic strain amplifiers are frequently used for stress measurement with strain gages. That is because the carrier type dynamic strain amplifier can conduct high precision measurement since it is highly resistant against hum noise from the power supply frequency in principle and is free from the thermoelectomotive force even if a metal contact is used in wiring to a Wheatstone bridge for measuring.A problem of the carrier type dynamic strain amplifier is generation of Capacitive component (hereinafter referred to as the C component) in an input cable connecting from the amplifier to the input sensor (Wheatstone bridge for measuring). The C component varies with cable length, cable materials, or ambient temperature change. The aforementioned changing adversely affects the stability of the amplifier. In this paper, we realize and analyze the method that increases the stability of amplifier by detecting, eliminating and self tracking the above C component constantly. Used carrier frequency at 12kHz and 28kHz.We made amplifiers with noise resistant and wide band frequency of measurement range and verified the theory of the Capacitance Self Tracing with the above amplifiers.

測定ブリッジ4辺のC分に対応した新CST方式動ひずみ測定器

測定ブリッジ4辺のC分に対応した新CST方式動ひずみ測定器

A Dynamic Source-Follower Integrator and Its Application to .DELTA..SIGMA. Modulators

A switched-capacitor integrator based on dynamic source follower amplifiers has been proposed. Integrator operation has been confirmed and analyzed by assuming 0.18-µm CMOS technology. The integrator can reduce the number of elements considerably compared with conventional ones using operational amplifiers. As a result, the power dissipation of proposed integrator can be reduced to approximately one-eighth that of conventional integrators. The integrator is applied to a second-order ΔΣ modulator, and its successful operation has been confirmed by transistor-level circuit simulation.

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm2.

Compensating unflattened WDM chips spectra using dynamic backward-pumped fiber Raman amplifiers technology

Fiber Raman amplifiers (FRAs) with multiple pumps are proposed to realize dynamic gain equalization for a spectral chips signal with a non-flattened broadband light source (BLS) in a spectrum-sliced wavelength-division multiplexing (WDM) network. In FRAs with multiple pumps, the gain profile can be adjusted via appropriate specification of the relative position of the pump wavelengths and the power of the pump waves. This paper combines a pump-power control algorithm and a genetic algorithm (GA) to establish the optimal pump spectrum for any specified gain spectrum in the WDM system. The method flattens the power spectra of WDM chips by identifying the optimal pump wavelengths and pump power of backward-pumped FRAs. It avoids the conventional requirement for time-consuming trial-and-error adjustments or intensive numerical simulations. Simulation results show that the scheme is simple, effective, and applicable for various BLSs in a spectrum-sliced WDM transmitter.

Design and Simulation of a 12-Phase Flywheel Energy Storage Generator System With Linearly Dynamic Load

Based on an original 12 kW 12-phase synchronous generator system, this paper presents the design scheme and computationally efficient simulation model of a 12-phase flywheel energy storage generator system with linearly dynamic load. In the designed system, the module functions of linearly dynamic load and excitation power amplifier are respectively performed by a Buck converter and full-bridge converter, and a joint algorithm of feedforward and feedback is adopted in the innovative excitation controller module. The system simulation model is built in EMTDC environment, where the machine models are obtained from secondary development in FORTRAN language. The simulation results show that all the designed modules can fulfill their basic functions, the active power of linearly dynamic load increases at the expected rate, the control precision and response speed of the system are satisfactory, and the solution of system simulation model is exact and fast.

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

High-efficiency dynamic supply CMOS audio power amplifier for low-power applications

This paper describes the analysis and design of a dynamic supply CMOS audio power amplifier for low-power applications. The dynamic supply technique is used to increase the efficiency of a class AB power amplifier. The polarization of its output stage is adaptive so that the maximum efficiency enhancement can be achieved without jeopardizing the linearity of the system. Two types of adaptive polarization are proposed and compared. A concept of power supplies switching is also proposed. Simulation results are presented showing that an efficiency of 53.6% at a total harmonic distortion (THD) of less than 0.1% can be achieved, whereas the maximal theoretical value for a class AB amplifier is approximately 33.3%.