Duobinary Transceiver Research Articles

A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer

In this article, we propose a duobinary transceiver for graphics double-data-rate (GDDR) memory interfaces. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver (Rx) reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer (EQ). To compensate for the channel loss, the transmitter is composed of a three-tap feed-forward EQ, and the Rx employs a continuous-time linear EQ. Also, an EQ adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate at 21 Gb/s with 1.42 mW/Gb.

A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface

A duo-binary signaling has been applied to both transmitter and receiver for high-speed low-power DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The voltage-mode driver is used in this brief, because it generates more linear output voltage than the current-mode driver for the duo-binary signaling at low supply voltage. A time-based receiver is used for high-speed operation at low supply voltage. A 1-tap look-ahead decision-feedback equalizer scheme was applied to the time-based receiver for the duo-binary decoding operation. The test chip fabricated in a 28 nm low-power CMOS process gives the energy efficiency of 0.41 pJ/b at 12 Gb/s with a 25 cm-long FR-4 micro-strip line and the supply voltage of 0.75V.

Recent Trends on High-Speed Duobinary Transceiver Architecture

Recent Trends on High-Speed Duobinary Transceiver Architecture

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks

Duobinary modulation is a robust and attractive coding format for high-speed serial data transmission because it allows an excellent tradeoff between speed, noise and power. However, conventional architectures reported in the literature performing the necessary precodification in a duobinary transceiver suffer from a severe vulnerability to glitches that limits their performances at high data rates. This study presents a new precoder scheme that overcomes this limitation with a very small design, area and power consumption, and a time-domain analysis that confirms the advantages of the proposed solution. The proposed precoder has been implemented in a full duobinary transceiver fabricated in a 0.13-μm partially depleted-silicon on insulator CMOS technology that works at 10 Gb/s. The fabricated precoder consumes 13.8 mW and the decoder consumes 23.2 mW from a single supply of 1.2 V. Experimental results are provided for a simulated channel of 50-m plastic optical fiber.

Improved Precoder Architecture for Duobinary Transceivers

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW.

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

A low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3" FR4 microstrip line, and at 7 Gb/s with a 0.6" FR4.

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission

A unique bit-edge equalization (BEE) method for mitigating intersymbol interference (ISI) in high-speed backplane applications is presented. Using a least-mean-square (LMS) adaptive algorithm as a receiver (RX) error convergence engine, the proposed BEE method aims to optimize the bit-edge amplitudes by equalizing only the edges of data bits with an adjustment of the sampling points where the error information is collected. This adjustment of sampling points in turn changes the error information and affects filter coefficients for pulse amplitude modulation. As a result, the channel's far-end 3-level bit-edge eye diagrams can be optimized. This proposed BEE method employs transmitter (TX) pre-coding in conjunction with TX pre-emphasis using a symbol-spaced FIR (SSF) filter. In this work, a detailed analytical comparison of the proposed BEE transceiver architecture with the conventional NRZ bit-centre equalization (BCE) and duobinary transceiver architectures is presented. The simulation results demonstrate that at 10+Gbps data rates, the proposed BEE is the most effective method for mitigating ISI in relatively high-loss channels.

Optimal equalization for reducing the impact of channel group delay distortion on high-speed backplane data transmission

Abstract Channel group delay distortion represents the transmission channel's phase dispersion, which results in signal distortion and adds intersymbol interference (ISI) to the received data eyes in addition to amplitude attenuation. Despite the fact that channel group delay distortion is especially critical in high-speed backplane applications, its effects have not been discussed in detail previously in the literature. This paper presents a study of the impacts of channel group delay distortion on high-speed backplane data transmissions. Equalization strategies for reducing the impact of group delay distortion are explored. A unique bit-edge equalization (BEE) scheme is presented that reduces the impact of channel group delay distortion by compressing the data spectrum in conjunction with optimizing the sampling phase. With transmitter (TX) pre-coding, the proposed BEE employs a 5-post-tap conventional symbol-spaced FIR (SSF) filter as the TX pre-emphasis, eliminates the need for a “delay and add” duobinary filter as in the conventional duobinary transceiver, and is more compatible with the bit-centre equalization (BCE) scheme. In this work, a typical Tyco 34-inch FR4 backplane channel is used as the comparison benchmark. A Matlab script based link simulation tool is used to evaluate the link performance. The optimality of the proposed BEE in reducing the impact of channel group delay distortion and mitigating ISI is demonstrated at a data rate as high as 12 Gbps.

CMOS Duobinary Transceiver for Multigigabit Communications

This work presents a CMOS transceiver for amplitude duobinary modulation over an equalized 50-m step-index plastic optical fiber (SI-POF). Both duobinary precoder and decoder have been fabricated in 0.18-μm CMOS technology, enabling a bandlimited system of 700 MHz to operate at 3.125 Gbps with a consumption of 28.4 mW.