Dummy Capacitor Research Articles

A 1V 200kS/s 10-bit Successive Approximation ADC for a Sensor Interface

A 200kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43dB for a 99.01kHz analog input signal at a sampling rate of 200kS/s. The power consumption and core area are 5µW and 0.126mm2, respectively. The FoM is 47fJ/conversion-step.

Si-based sensor for virus detection

This paper describes the development of a sensor for the detection of viruses. The detection scheme uses sense and dummy capacitors and a sense amplifier circuit to compare capacitance values. The presence of sufficient biological material within the sense capacitor alters the sense amplifier output. This promising approach has the potential to more rapidly test for the presence of virus using an IC platform.

A Two-Stage Spark Gap for Blumlein-Driven Transversely Excited Atmospheric Nitrogen Laser

A two-stage spark gap is used to implement a two-stage Blumlein circuit for the efficient operation of a transversely excited atmospheric nitrogen laser. This enables a more compact circuit arrangement which employs an array of doorknob capacitors as the dummy capacitors instead of large parallel-plate capacitors but maintains a comparable laser output performance.

A 76-mm/sup 2/ 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-/spl mu/m 2-metal CMOS technology. A small die of 76 mm/sup 2/ and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 /spl mu/m/sup 2/; 2) a new hierarchical wordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacitor size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain architecture with these new techniques reduces die size to 65% of that of the conventional FeRAM. Moreover a ferroelectric capacitor overdrive scheme enables sufficient polarization switching, without overbias memory cell array. This scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5-V V/sub dd/ operation. Thanks to fast cell plateline drive of chain architecture, the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 ns, at 3.0 V so far reported.

A high-speed current-multiplexed sample-and-hold amplifier with low hold step

A monolithic high-speed sample-and-hold amplifier is described. It minimizes the hold step via a new circuit architecture. This design takes advantage of the speed of open-loop sample-and-hold circuits during the sample mode and cancellation of charge injection by duplicating and feeding it through a second amplifier during the hold mode. The unique feature of the design is an acquisition time of 150 ns to 0.01% of a 10-V step including the time required for all internal nodes to settle after the hold command is given. Aperture uncertainty is less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip hold and dummy capacitors and the die size is 8.548 mm/sup 2/ on a junction-field-effect-transistor (JFET) plus complementary bipolar process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>