Dual-socket Intel Research Articles

Integrating batched sparse iterative solvers for the collision operator in fusion plasma simulations on GPUs

Batched linear solvers, which solve many small related but independent problems, are increasingly important for highly parallel processors such as graphics processing units (GPUs). GPUs need a substantial amount of work to keep them operating efficiently and it is not an option to solve smaller problems one-by-one. Because of the small size of each problem, the task of implementing a parallel partitioning scheme and mapping the problem to hardware is not trivial. In recent history, significant attention has been given to batched dense linear algebra. However, there is also an interest in utilizing sparse iterative solvers in a batched form.An example use case is found in a gyrokinetic Particle-In-Cell (PIC) code used for modeling magnetically confined fusion plasma devices. The collision operator has been identified as a bottleneck, and a proxy app has been created for facilitating optimizations and porting to GPUs. The current collision kernel linear solver does not run on the GPU—a major bottleneck. As these matrices are sparse and well-conditioned, batched iterative sparse solvers are an attractive option.A batched sparse iterative solver capability has recently been developed in the Ginkgo library. In this paper, we describe how Ginkgo's batched solver technology can integrate into the XGC collision kernel and accelerate the simulation process. Comparisons for the solve times on NVIDIA V100 and A100 GPUs and AMD MI100 GPUs with one dual-socket Intel Xeon Skylake CPU node with 40 cores are presented for matrices from the collision kernel of XGC. Further, the speedups observed for the overall collision kernel are presented in comparison to different modern CPUs on multiple supercomputer systems. The results suggest that Ginkgo's batched sparse iterative solvers are well suited for efficient utilization of the GPU for this problem, and the performance portability of Ginkgo in conjunction with Kokkos (used within XGC as the heterogeneous programming model) allows seamless execution on exascale-oriented heterogeneous architectures.

Semi-Lagrangian Vlasov simulation on GPUs

In this paper, our goal is to efficiently solve the Vlasov equation on GPUs. A semi-Lagrangian discontinuous Galerkin scheme is used for the discretization. Such kinetic computations are extremely expensive due to the high-dimensional phase space. The SLDG code, which is publicly available under the MIT license, abstracts the number of dimensions and uses a shared codebase for both GPU and CPU based simulations. We investigate the performance of the implementation on a range of both Tesla (V100, Titan V, K80) and consumer (GTX 1080 Ti) GPUs. Our implementation is typically able to achieve a performance of approximately 470 GB/s on a single GPU and 1600 GB/s on four V100 GPUs connected via NVLink. This results in a speedup of about a factor of ten (comparing a single GPU with a dual socket Intel Xeon Gold node) and approximately a factor of 35 (comparing a single node with and without GPUs). In addition, we investigate the effect of single precision computation on the performance of the SLDG code and demonstrate that a template based dimension independent implementation can achieve good performance regardless of the dimensionality of the problem.

Tensor-optimized hardware accelerates fused discontinuous Galerkin simulations

In recent years the computation/memory balance of processors has been continuously shifting towards computation. The rise of Deep Learning, which is based on matrix multiplications, accelerated this path, especially in terms of single precision and lower precision computation. An important research question is if this development can be leveraged for traditional HPC. In this work we demonstrate that a high order discontinuous Galerkin solver for seismic wave propagation can execute in single precision without loss of modeling accuracy. Additionally, we extended its kernels to support the Intel Knights Mill CPU with 14 TFLOPS of tensor-optimized single precision performance. This allows us to exploit the hardware’s special computation capabilities, even in a regular HPC application with sparse linear algebra kernels. At the cluster-level, Knights Mill can obtain the same application performance as the latest top-bin dual socket Intel Xeon Platinum nodes. Compared to the HPC-focused Knights Landing processor, speed-ups of up to 1.6 × are possible, depending on the configuration of the solver. Additionally, we are able to increase the throughput of a quadrature-free discontinuous Galerkin method for seismic simulations by 4.2 × , when comparing our solver’s single precision and fifth order performance to the SC 2017 best-paper award winning work.

Harris corner detection on a NUMA manycore

Corner detection is a key kernel for many image processing procedures including pattern recognition and motion detection. The latter, for instance, mainly relies on the corner points for which spatial analyses are performed, typically on (probably live) videos or temporal flows of images. Thus, highly efficient corner detection is essential to meet the real-time requirement of associated applications. In this paper, we consider the corner detection algorithm proposed by Harris, whose the main work-flow is a composition of basic operators represented by their approximations using 3 × 3 matrices. The corresponding data access patterns follow a stencil model, which is known to require careful memory organization and management. Cache misses and other additional hindering factors with NUMA architectures need to be skillfully addressed in order to reach an efficient scalable implementation. In addition, with an increasingly wide vector registers, an efficient SIMD version should be designed and explicitly implemented. In this paper, we study a direct and explicit implementation of common and novel optimization strategies, and provide a NUMA-aware parallelization. Experimental results on a dual-socket INTEL Broadwell-E/EP show a noticeably good scalability performance.

Parallel BRDF-based infrared radiation simulation of aerial targets implemented on Intel Xeon processor and Xeon Phi coprocessor

The infrared (IR) radiance of an aerial target owing to the reflection of the external sources including the sun, atmosphere and the earth’s surface is a key factor to consider in the modeling and simulation of the IR image in the studies of target detection and tracking, guidance and camouflage. Since the radiations of atmosphere and the earth’s surface spread in the whole space and over a wide spectrum, the geometrical shape of targets is complex, and their surfaces are usually non-Lambertian, serial implementation on a CPU platform is time-consuming, and thus, the acceleration of the calculation process is desired in engineering projects. The inherent parallelism that the reflection of radiations incident from different directions in each spectral wavelength can be calculated in parallel in this problem encourages us to accelerate it on multi-core platforms, which are common nowadays. In this work, a dual-socket Intel Xeon E5-2620 nodes running at 2.00 GHz are utilized first. Subsequently, implementations using native and offload modes on the Intel Xeon Phi 5110p coprocessor are described in detail. In both the host-only and Xeon Phi-based implementations, the OpenMP directives are used. Compared to their single-threaded counterpart, the host-only version is 9.7x faster. By increasing the scalability and vectorization, speedups obtained in the native and offload mode implementations were 13.8x and 13.0x, respectively. Our results show that the Xeon Phi’s performance on calculating the target’s reflected radiance of background radiation is promising in the IR image simulation.

Enhanced multiobjective population-based incremental learning with applications in risk treaty optimization

The purpose of this paper is to revisit the Multiobjective Population-Based Incremental Learning method and show how its performance can be improved in the context of a real-world financial optimization problem. The proposed enhancements lead to both better performance and improvements in the quality of solutions. Its performance was assessed in terms of runtime and speedup when parallelized. Also, metrics such as the average number of solutions, the average hypervolume, and coverage have been used in order to compare the Pareto frontiers obtained by both the original and enhanced methods. Results indicated that the proposed method is 22.1 % faster, present more solutions in the average (better defining the Pareto frontier) and often generates solutions having larger hypervolumes. The enhanced method achieves a speedup of 15.7 on 16 cores of a dual socket Intel multi-core machine when solving a Reinsurance Contract Optimization problem involving 15 Layers or sub-contracts.

Comparison of the Parallel Fast Marching Method, the Fast Iterative Method, and the Parallel Semi-ordered Fast Iterative Method

Solving the eikonal equation allows to compute a monotone front propagation of anisotropic nature and is thus a widely applied technique in different areas of science and engineering. Various methods are available out of which only a subset is suitable for shared-memory parallelization, which is the key focus of this analysis. We evaluate three different approaches, those being the recently developed parallel fast marching method based on domain decompositioning, the inherently parallel fast iterative method, and a parallel approach of the semi-ordered fast iterative method, which offers increased stability for variations in the front velocity as compared to established iterative methods. We introduce the individual algorithms, evaluate the accuracy, and show benchmark results based on a dual socket Intel Ivy Bridge-EP cluster node using C++/OpenMP implementations. Our investigations show that the parallel fast marching method performs best in terms of accuracy and single thread performance and reasonably well with respect to parallel efficiency for up to 8-16 threads.

Data mining on vast data sets as a cluster system benchmark

SummaryComparing different (accelerated) cluster architectures by a single application is a tough piece of work because this application has to be optimized with respect to platform‐dependent features. In this work, we demonstrate such an optimization for a data mining algorithm which solves regression and classification problems on vast data sets. Our technique is based on least squares regression, and its major component is the iterative matrix‐free solution of a linear system of equations. By processing data sets ranging from several hundreds of thousands instances to multi‐million data points in strong‐scaling and weak‐scaling settings, we are able to estimate the amount of parallelism needed to unleash the performance of classic CPU‐based machines and clusters employing Intel Xeon Phi coprocessors and NVIDIA Kepler GPUs. Only in strong‐scaling experiments, GPUs and coprocessors suffer from their tremendous amount of needed parallelism and get outperformed by dual socket Intel Sandy Bridge nodes at large scale (more than 64 nodes/accelerators). However, in weak‐scaling scenarios, a speed‐up larger than 2X over an entire CPU node can be achieved by a single accelerator. Copyright © 2015 John Wiley & Sons, Ltd.

A dynamically configurable coprocessor for convolutional neural networks

Convolutional neural networks (CNN) applications range from recognition and reasoning (such as handwriting recognition, facial expression recognition and video surveillance) to intelligent text applications such as semantic text analysis and natural language processing applications. Two key observations drive the design of a new architecture for CNN. First, CNN workloads exhibit a widely varying mix of three types of parallelism : parallelism within a convolution operation, intra-output parallelism where multiple input sources (features) are combined to create a single output, and inter-output parallelism where multiple, independent outputs (features) are computed simultaneously. Workloads differ significantly across different CNN applications, and across different layers of a CNN. Second, the number of processing elements in an architecture continues to scale (as per Moore's law) much faster than off-chip memory bandwidth (or pin-count) of chips. Based on these two observations, we show that for a given number of processing elements and off-chip memory bandwidth, a new CNN hardware architecture that dynamically configures the hardware on-the-fly to match the specific mix of parallelism in a given workload gives the best throughput performance. Our CNN compiler automatically translates high abstraction network specification into a parallel microprogram (a sequence of low-level VLIW instructions) that is mapped, scheduled and executed by the coprocessor. Compared to a 2.3 GHz quad-core, dual socket Intel Xeon, 1.35 GHz C870 GPU, and a 200 MHz FPGA implementation, our 120 MHz dynamically configurable architecture is 4x to 8x faster. This is the first CNN architecture to achieve real-time video stream processing (25 to 30 frames per second) on a wide range of object detection and recognition tasks.