Dual Power Supply Research Articles

Novel Sensor Design and Application for Detection of Dangerous Contaminated Marine Biotoxins

We have developed a novel planar interdigital sensing system: using a microcontroller and local fabricated circuits with dual supply and signal processing for data acquisition. The first prototype is called seafood inspection tool or SIT consist of a SiLab C8051F020 microcontroller, a signal processing circuit, novel planar interdigital sensor, an expansion board and dual power supply circuit. A user friendly software was also developed to make SIT easy to be used by users who has a little technical knowledge. SIT was developed to be tested by the fisherman who can do a pre-screening process of the mussels at their ranch site.Our main objective is to sense the presence of dangerous contaminated acid in mussels and other seafoods.

Design of Dual-Power Supply Automatic Switching Device without Disturbance

The dual power supply system is widely used in our daily life. When power instantaneously switched between the main power and the stand-by power supply, the voltage fluctuations had the varying degree influence on machines. Based on the principle of correlation coefficient of two waveforms and instantaneous reactive power theory, the dual-power supply automatic and instantaneous switching device without disturbance is provided in this paper. The equipment could identify and isolate the broken-down power source in 5ms. At the same time, power supply keeps continuous meeting the requirements of power quality without voltage drop.

Requirement Analyses for Hybrid Bus Power Supply

A hybrid bus power supply project is presented in this paper, compared with the characters of current bus power supply. The paper establishes a dual power supply ( engine and bus power supply) hybrid bus power distribution simulation model, and analyses the requirements of the power supply for hybrid bus. In order to analyses the requirements of HEV bus power supply, the model is under the theory of HEV control strategies.

An Ultra Low-Power Solution for EEPROM in Passive UHF RFID Tag IC With a Novel Read Circuit and a Time-Divided Charge Pump

A dual power supply ultra low-power 1 kbits EEPROM for passive UHF RFID is presented. The read power source is 1 V, while the write power source is 1.65 V, which is only activated in the write mode. To reduce the power of the read circuit without impacting the performance, a pre-charge scheme, a feedback scheme and a self-detect circuit, combined with a special read time sequence are adopted. A time-divided charge pump is proposed to reduce the current surge of the charge pump at the startup phase. The EEPROM IP has been fabricated in a SMIC 0.18 μm 2P4M EEPROM process. The die size of the proposed EEPROM IP is 0.12 mm2. The read and write currents of the EEPROM IP are 1.18 μA and 33 μA respectively. Under a 110 temperature variation, the power variation of the read operation is 15%. The EEPROM IP is then verified in a full UHF RFID chip. Tested by a commercial reader at 4 W EIRP, the maximum read and write communication ranges are 6 m and 3 m respectively. The measured voltage drop of the output of rectifier Vrect caused by the current surge of the charge pump is smaller than 50 mV.

Design of Dual DC Regulated Power Supply Based on MCU dsPIC30F3011

Traditional dual DC power supply used most of the linear power, which is lack of self-protection function, a high failure rate and the maintenance workload. To introduce a dual DC regulated power supply based on MCU design, the main circuit design using diodes to complete AC/DC conversion, and then through IGBT chopper adjustment, to achieve the DC/DC conversion outputs DC voltage. The control circuit uses dsPIC30F3011 as core, in accordance with the time optimal and PID control to achieve PWM regulation. Experiments results show that the design circuit has failed to self-protection and LCD display, in order to accurately and quickly repair the fault.

A four-channel parallel 40 Gb/s laser diode voltage driver in 0.18-μm CMOS

This article describes the design of a four-channel parallel 40 Gb/s laser diode voltage driver (LDVD) circuit using 0.18-μm CMOS technology.The LDVD circuit consists of input buffer stage, preamplifier stage, and output driver stage. The LDVD uses dual power supplies, including the 1.8-V supply in the preamplifier stage and the 3.5-V supply in the output driver stage. To increase the bandwidth, the preamplifier stage is made up of two-stage cascaded differential amplifiers. The output driver circuit uses the RC negative feedback and capacitively coupled current amplifier (C3A) structure to speed up the operation of laser diode. The isolation has been carefully taken to avoid the cross-talk issues among channels. Experimental results show that each channel of the LDVD can work at 10 Gb/s rate, and the output current swing is over 10 mA. The total power dissipation is 450 mW, and the chip area is 460 × 1230 μm2. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1540–1543, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27635

A Survey of Light Emitting Diode (LED) Display Board

In this paper an overview of different Light Emitting Diode (LED) display boards is presented. The enhanced LED plugs in all the loop holes in the existing product. Global Service for Message (GSM) based LED Display Board is a model for displaying notices or messages at places that require real-time noticing, by sending messages in the form of Short Message Service (SMS) through mobile. This paper proposes an idea to develop a sign board in which the messages are continuously running, where it empowers the user to change the messages using SMS instantaneously and also desk bound device such as PC or laptop. It has a dual system in terms of changing message display. It uses dual power supply such as solar power and Alternative Current (AC) power which creates the ability to work at any situation. The new design includes a motion detector which switches off the system automatically after working hours and will switch on automatically if any motion is sensed by the motion detector after the programmed working hours. This paper is a comprehensive overview of the literature and it does not contain implementation results.

A Survey of Light Emitting Diode (LED) Display Board.

In this paper an overview of different Light Emitting Diode (LED) display boards is presented. The enhanced LED plugs in all the loop holes in the existing product. Global Service for Message (GSM) based LED Display Board is a model for displaying notices or messages at places that require real-time noticing, by sending messages in the form of Short Message Service (SMS) through mobile. This paper proposes an idea to develop a sign board in which the messages are continuously running, where it empowers the user to change the messages using SMS instantaneously and also desk bound device such as PC or laptop. It has a dual system in terms of changing message display. It uses dual power supply such as solar power and Alternative Current (AC) power which creates the ability to work at any situation. The new design includes a motion detector which switches off the system automatically after working hours and will switch on automatically if any motion is sensed by the motion detector after the programmed working hours. This paper is a comprehensive overview of the literature and it does not contain implementation results.

A Design of Intelligent Car Based on STC89S52 Single Chip Microcomputer

With the development of production automation and science and technology level, the intelligent level of the car is continuously improved. For intelligent car, with STC89S52 single chip microcomputer as its core of control, the direction and speed of it is controlled by the collection and processing of the signals from various kinds of transducers in the forward path. Therefore, the functions of automatic identification of black guide line applied to rapid and steady running status of the car and the obstacle color discrimination applied to direction selection during the course of running and other relevant functions can be realized. In this system, a DC motor is used for the forward and steering movement of the car, a LCD1602 is used for the display of its travel time, and a dual power supply by which system stability can be enhanced is used for the motor and control system respectively. Besides, the system control software is designed to be a combination of software and hardware, through which the anticipated functions of the car is ultimately realized.

Safe and consistent method of spot-welding platinum thermocouple wires and foils for high temperature measurements

A low-voltage (mV) electronically triggered spot welding system for fabricating fine thermocouples and thin sheets used in high-temperature characterization of materials' properties is suggested. The system is based on the capacitance discharge method with a timed trigger for obtaining reliable and consistent welds. In contrast to existing techniques based on employing high voltage DC supplies for charging the capacitor or supplies with positive and negative rails, this method uses a simple, standard dual power supply available at most of the physical laboratories or can be acquired at a low cost. In addition, an efficient and simple method of fabricating non-sticking electrodes that do not contaminate the weld area is suggested and implemented.

Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

Limited energy consumption in multimedia requires very low power circuits. In this paper we focused on leakage current minimization in single static random access memory (SRAM) cell in 90nm complementary metal oxide semiconductor (CMOS) technology. The leakage current mainly consists of sub threshold leakage current and gate leakage current in 90nm CMOS technology. So minimizing the sub threshold leakage current and gate leakage current is most important aspect in low power memory design. This work presents a technique based on dual threshold voltage (Vt), dual gate oxide thickness (tox) and dual power supply (Vdd) assignment together to minimize gate leakage and sub threshold current of SRAM cell.Simulation results using 90nm CMOS technology show that this technique can reduce the total leakage current dissipation of a single SRAM cell by more than 75% with less delay penalty.

Dynamic Bridge Piezoelectric Amplifiers with Signal Generator

Piezoelectric amplifier is a very important part of the piezoelectric actuator. Not only positioning accuracy, but also dynamic performance and power are demanded more and more highly. At present piezoelectric amplifier are mainly used in static applications, power and frequency response are usually incompatible. This paper developed a new type of piezoelectric amplifier to meet high demand for dynamic, which takes dual-power supply, bridge-output to achieved slew rate, power were doubled, and maintain a wide frequency range at the same time. Controller implements DDS unit through FPGA, which could achieve sine, triangle, square and sawtooth.

High-Efficiency DC–DC Converter With Two Input Power Sources

The aim of this study is to develop a high-efficiency converter with two input power sources for a distributed power generation mechanism. The proposed converter can boost the varied voltages of different power sources in the sense of hybrid power supply to a stable output dc voltage for the load demand. An auxiliary circuit in the proposed converter is employed for achieving turn-ON zero-voltage switching (ZVS) of all switches. According to various situations, the operational states of the proposed converter can be divided into two states including a single power supply and a dual power supply. In the dual power-supply state, the input circuits connected in series together with the designed pulsewidth modulation can greatly reduce the conduction loss of the switches. In addition, the effectiveness of the designed circuit topology and the ZVS properties are verified by experimental results, and the goal of high-efficiency conversion can be obtained.

A Low-Power Block-Based CMOS Image Sensor With Dual VDD

A novel low-power image sensor with dual analog power supply 1.8 and 1.1 V during image capture stage is proposed. Different from a traditional imager having a unique analog power for image capture, the proposed imager works on blocks of 8 × 8 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, high supply voltage will be chosen to achieve high imaging performance; otherwise, low supply voltage will be used to save power. In addition, the power gating method is applied to the additional computation circuits to save power further. Theoretical analysis and simulation results by Matlab and Cadence are given to demonstrate the efficiency of the proposed methodology. The amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB). The chip is implemented in TSMC 0.18 μm CMOS technology and simulated by Spectre Cadence. The total power consumption of the additional computation logic is only about 7.0 μW .

The study on the power management system in a fuel cell hybrid vehicle

This paper presents a model of a hybrid electric vehicle, based on a primary proton exchange membrane fuel cell (PEMFC) and an auxiliary Li-ion battery, and its dynamics and overall performance. The power voltage from the fuel cell is regulated by a DC/DC converter before integrating with the Li-ion battery, which provides energy to the drive motor. The driving force for propelling the wheels comes from a permanent magnet synchronous motor (PMSM); where the power passes through the transmission, shaft, and the differential.The mathematical model, comprising the PEMFC, Li-ion battery, PMSM, and vehicular structure, was modeled in MATLAB/Simulink. A power management model was incorporated in the system such that the power output varies in different conditions; including high power, low power, standard power, and charge modes. By changing the speed of the accelerator, the relation between the output of dual power supply, hydrogen consumption, and Li-ion battery’s state of charge was observed.The power management model is validated against the ECE40 driving cycle. The performance of the fuel cell hybrid vehicle is evaluated. The operation modes in the vehicle show a close match with the proposed power management system. Additionally, the hybrid ratio is measured to evaluate the overall efficiency. The results indicate that the hybrid ratio shows little correlation with efficiency. However, the higher the power of the fuel cell, the higher the hydrogen consumption.

Design of a 32-Channel EEG System for Brain Control Interface Applications

This study integrates the hardware circuit design and the development support of the software interface to achieve a 32-channel EEG system for BCI applications. Since the EEG signals of human bodies are generally very weak, in addition to preventing noise interference, it also requires avoiding the waveform distortion as well as waveform offset and so on; therefore, the design of a preamplifier with high common-mode rejection ratio and high signal-to-noise ratio is very important. Moreover, the friction between the electrode pads and the skin as well as the design of dual power supply will generate DC bias which affects the measurement signals. For this reason, this study specially designs an improved single-power AC-coupled circuit, which effectively reduces the DC bias and improves the error caused by the effects of part errors. At the same time, the digital way is applied to design the adjustable amplification and filter function, which can design for different EEG frequency bands. For the analog circuit, a frequency band will be taken out through the filtering circuit and then the digital filtering design will be used to adjust the extracted frequency band for the target frequency band, combining with MATLAB to design man-machine interface for displaying brain wave. Finally the measured signals are compared to the traditional 32-channel EEG signals. In addition to meeting the IFCN standards, the system design also conducted measurement verification in the standard EEG isolation room in order to demonstrate the accuracy and reliability of this system design.

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit, 100 MS/s CMOS digital-to-analog converter (DAC). Analog background self-calibration based on the concept of analog current trimming is introduced. A constant clock load switch driver, a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance. The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33 × 0.97 mm2 of the core area. The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog, respectively. The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB, respectively. The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.

Low power design of a field sequential color LCoS chip

The low power design of a field sequential color (FSC) liquid crystal on silicon (LCoS) chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design, that is, the supply for part of driving circuits is 3.3 V, and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also, an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 µm CMOS process and its power consumption is only about 300 mW.

Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

This paper describes design of high energy efficiency 32 bit parallel processor core using instructtion-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

Low-Power 512-Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.