Dual-port Static Random Access Memory Research Articles

Configurable in-memory computing architecture based on dual-port SRAM

In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit multiply and accumulate (MAC) and XOR accumulation (XORA). The architecture was simulated using a 28-nm Complementary Metal Oxide Semiconductor Process, demonstrating a minor standard deviation of 9.41 mV in bit line voltage at the SS process corner, as evidenced by Monte Carlo simulation. Energy expenditure for the MAC, XORA, and XORE, was found to be 1.65, 1.46, and 9.02 fJ/ops respectively at the TT process corner. Furthermore, the presented architecture showed considerable energy efficiency, with MAC, XORA, and XORE operations achieving energy efficiency values of 604.9, 682.7, and 110.8 TOPS/W respectively, at a supply voltage of 0.9 V at the TT process corner.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (Iread) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (Vmin) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology

Multiported high-performance on-die memories occupy significantly more die area than a comparable single-port memory. Among various multiport memory topologies, the 1-read (R), 1-write (W) 8-transistor (T) Static Random Access Memory (SRAM) with a decoupled read port allows separate optimization of the read and write ports when organized without interleaved logical columns. This enables a lower minimum operating voltage ( $V_{\mathrm{ min}}$ ) compared with other dual-port SRAMs that require ports optimized for read stability and write operations. However, the 1R1W 8T SRAM often employs large signal, hierarchical bitline sensing to achieve high performance due to the nondifferential read bitline. This large-signal read architecture necessitates frequently placed local bitline sensing circuits, degrading the array bit density. In this paper, we present two sense amplifier (SA) techniques for small-signal pseudo-differential sensing to facilitate 256 bits per bitline achieving an 8T SRAM array density of 5.6 Mb/mm $^{2}\vphantom {^{\int ^\int }}$ in 14 nm FinFET CMOS. The first design employs a charge sharing SA scheme to generate a reference voltage ( $V_{\mathrm{ REF}}$ ) by leveraging the capacitance of otherwise unused metal tracks over the bitcell column. The second design utilizes an asymmetric SA in which the read bitline precharged to $V_{\mathrm{ CC}}$ in the unselected sector acts as a reference voltage and the active bitline side is intentionally upsized to skew the SA. High volume measurement results demonstrate 560 mV $V_{\min }$ at 400 MHz/−10 °C and reaches 2.21 GHz at 1 V supply.

Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at higher voltage and temperature. Design is implemented in CMOS 32NM low power technology for dual port (DP) SRAM bit cell 0.390u2 (DP390) having a normal operating range from 0.9 to 1.1 V, extended to 0.75-1.1 V by utilizing proposed WA circuit. This design has an area overhead of 4.5%. Write cycle performance improvement and dynamic power reduction achieved is 10% and 8%, respectively, at 0.9 V with respect to the design without WA.

Design of an 8-cell Dual Port SRAM in 0.18-μm CMOS Technology

Low power and low area Static Random Access Memory (SRAM) is essential for System on Chip (SoC) technology. Dual-Port (DP) SRAM greatly reduces the power consumption by full current-mode techniques for read/write operation and the area by using Single-Port (SP) cell. An 8 bit DP-SRAM is proposed in this study. Negative bit-line technique during write has been utilized for write-assist solutions. Negative voltage is generated on-chip using capacitive coupling. The proposed circuit design topology does not affect the read operation for bit interleaved architectures enabling high-speed operation. Designed in 0.18-μm CMOS process, the area is only 1.2 times of the SP-SRAM and its power is 1.3 times of the SP-SRAM when the two ports simultaneously work at the same frequency. Simulation results and comparative study of the present scheme with state of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption. The proposed negative bit- line technique can be used to improve the write ability of 6 T Single-Port (SP) as well as 8 T DP and other multiport SRAM cells.

A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances

Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption. We fabricated a 1-Mbit DP-SRAM with WA8T testchip using a 40-nm CMOS process. The proposed WA8T device achieved a 120-mV improvement in VDDmin with less than 1% area overhead.

FPGA based efficient on-chip memory for image processing algorithms

In Field Programmable Gate Array (FPGA) efficient utilization of on-chip Static Random Access Memory (SRAM) is extremely important for most applications especially for image processing. True Dual Port (TDP) SRAM and Single Port (SP) SRAM are typically available SRAMs for image processing algorithms. But in case of data access policy changes, the memories need to be redesigned. Hence on-chip memory architecture capable of scanning the data in different ways without redesigning is required. In the proposed sub-bank Dual Port (DP) memory architecture, SP SRAM has been modified to function as a TDP SRAM, with high throughput and less power consumption. It also provides higher level of abstraction suitable for image processing algorithms with the help of two-port memory control unit, clock and address generators. The proposed sub-bank memory architecture and its system is implemented and verified for Lapped Biorthogonal Transform based Low complexity Zerotree Codec (LBT-LZC), an image coding algorithm. By considering the significant factors such as resource utilization, time and power, the proposed system outperforms TDP SRAMs.

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

The increased device variations, lower supply voltages have enforced the usage of write-assist circuits in static random access memory (SRAMs) in the nano-complementary metal oxide semiconductor (CMOS) regime. Negative bit-line scheme during write has been found one of the most promising write-assist solutions. A new low power, negative bit-line scheme is presented. The presented negative bit-line technique can be used to improve the write ability of 6 T single-port (SP) as well as 8 T dual-port (DP) and other multiport SRAM cells. Negative voltage is generated on-chip using capacitive coupling. Only the bit-line on which a '0' is to be written is taken negative during write operation. The proposed circuit design topology does not affect the read operation for bit-interleaved architectures enabling high-speed operation. Simulation results and comparative study of the present scheme with state-of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption.