A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances

Abstract

Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption. We fabricated a 1-Mbit DP-SRAM with WA8T testchip using a 40-nm CMOS process. The proposed WA8T device achieved a 120-mV improvement in VDDmin with less than 1% area overhead.