Abstract
Simultaneous read and write operations without any disturbance is a fundamental expectancy from any dual port static random access memory (DPSRAM) cell design. The paper proposes a stable loadless 6T DPSRAM cell design with reduced port setup time as compared to that of standard 8T DPSRAM along with better read stability. The design has lower cycle time allowing SRAM to operate at higher frequencies and hence, more memory can be accessed in a given time. To preserve the data integrity, an optimum port setup time is calculated using best fit curve from regression plots with 95% confidence bounds. As port setup time is increased, voltage value for spurious logic reduces. The proposed design has port setup time of 1.6 picoseconds as compared to 7.2 picoseconds of 8T DPSRAM.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
