Here we proposes and optimizes a delta doped dual spacer negative capacitance TFET to improve ON current, steeper sub threshold slope, and ON to OFF current ratio. The inclusion of the delta layer and high K spacer on the source side improves the characteristics by increasing the electric field and lowering the surface potential at the source channel interface. The incorporation of the FE layer in the gate stack creates the negative capacitance effect and improves the performances due to voltage amplification process. Here, FE-HFO2 is taken as a ferroelectric material. A very high current ratio of the order 1.8 × 1012 with a substantially low average sub threshold swing of 18 mV/decade is achieved which make it suitable for low power applications. Finally, for optimized NCFETs, the influence of temperature (200 K–350 K) is examined at tfe = 5 nm for switching characteristics.