Dual-issue RISC Processor Research Articles

A novel hardware/software partitioning for SIMD-based real-time AVS video decoder

Decoding high-quality videos in real-time is becoming more and more difficult with the increasing resolution. In this paper, a novel hardware/software (HW/SW) partitioning is proposed with powerful SIMD (single instruction multiple data) instructions for the real-time AVS video decoder. Since most key functions that need large amounts of computations are optimized by SIMD instead of hardware, the distribution of workload between hardware and software is balanceable, and the performance of the video decoder is improved. Besides, the generality and programmability are also maintained. The proposed method is implemented on a 32-bit dual-issue RISC processor with 256-bit vector extension. The experimental results of conformation AVS test sequences show that the video decoder system can support the real-time decoding of AVS 1080p videos at 30 fps, and improve performance over 100 times compared to the original processor without the proposed method. Moreover, this approach could be easily applied to other video decoders, such as H.264 and VC-1.

A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor

A real-time system large-scale-integrated circuit (LSI) for digital video cassette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performance and can execute fixed-length data processing at the block level as well as processing at the macro-block level and above for the DVCR/MPEG-2. The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables. The dedicated hardware for video-block loading can process video-block data transfers with half-pel operations. The LSI size is 7.7/spl times/7.2 mm/sup 2/ in a 0.25-/spl mu/m CMOS process.

Single chip dual-issue risc processor for real-time MPEG-2 software decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.

Single Chip Dual---Issue RISC Processor for Real---Time MPEG---2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.