Abstract
A real-time system large-scale-integrated circuit (LSI) for digital video cassette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performance and can execute fixed-length data processing at the block level as well as processing at the macro-block level and above for the DVCR/MPEG-2. The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables. The dedicated hardware for video-block loading can process video-block data transfers with half-pel operations. The LSI size is 7.7/spl times/7.2 mm/sup 2/ in a 0.25-/spl mu/m CMOS process.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
