Dual In-line Memory Module Research Articles

SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging

The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing memory accesses, execution time, and energy consumption. The embedded NMP module in SARDIMM optionally supports a combination of FFT, IFFT, and matched filter operations of the RDA for range and azimuth compression. The operator within the NMP module accelerates the FFT by performing two radix-2 single butterfly operations in parallel. The NMP module was implemented and validated on a Xilinx UltraScale+ field-programmable gate array (FPGA) using Verilog-HDL. The acceleration performance of RDA for images of various sizes was evaluated through a simulator modified with gem5 and DRAMSim3 and achieved a 6.34–6.93× speedup and 41.9–48.2% energy savings.

ML-driven risk estimation for memory failure in a data center environment with convolutional neural networks, self-supervised data labeling and distribution-based model drift determination

With the trend towards multi-socket server systems, the demand for random access memory (RAM) per server increased. The consequence are more DIMM sockets per server. Since every dual in-line memory module (DIMM), which comprises a series of dynamic random-access memory integrated circuits, has a probability of failure, RAM issues became a dominant failure pattern for servers. The concept introduced in this work contributes to improving the reliability of data centers by avoiding RAM failures and mitigating their impact. For this purpose, an ML-driven framework is provided to estimate the probability of memory failure for each RAM module. The ML framework is based on structural information between correctable (CE) and uncorrectable errors (UE). In a common memory scenario, a corrupted bit within a module can be restored by redundancy using an error correction code (ECC), resulting in a CE. However, if there is more than one corrupted bit within a group of bits covered by the ECC, the information cannot be restored, resulting in a UE.Consequently, the related task requesting the memory content, and the corresponding service may crash. There is evidence that UEs have a CE history and structural relation between the CEs. However, for the case of UEs without a CE history or of a false decision of the ML framework, we extend the total framework by engineering measures to mitigate the impact of a UE by avoiding kernel panic and using backups. The engineering measures use a mapping between physical and logical memory addresses.

Design and Analysis of a Processing-in-DIMM Join Algorithm: A Case Study with UPMEM DIMMs

Modern dual in-line memory modules (DIMMs) support processing-in-memory (PIM) by implementing in-DIMM processors (IDPs) located near memory banks. PIM can greatly accelerate in-memory join, whose performance is frequently bounded by main-memory accesses, by offloading the operations of join from host central processing units (CPUs) to the IDPs. As real PIM hardware has not been available until very recently, the prior PIM-assisted join algorithms have relied on PIM hardware simulators which assume fast shared memory between the IDPs and fast inter-IDP communication; however, on commodity PIM-enabled DIMMs, the IDPs do not share memory and demand the CPUs to mediate inter-IDP communication. Such discrepancies in the architectural characteristics make the prior studies incompatible with the DIMMs. Thus, to exploit the high potential of PIM on commodity PIM-enabled DIMMs, we need a new join algorithm designed and optimized for the DIMMs and their architectural characteristics. In this paper, we design and analyze Processing-In-DIMM Join (PID-Join), a fast in-memory join algorithm which exploits UPMEM DIMMs, currently the only publicly-available PIM-enabled DIMMs. The DIMMs impose several key challenges on efficient acceleration of join including the shared-nothing nature and limited compute capabilities of the IDPs, the lack of hardware support for fast inter-IDP communication, and the slow IDP-wise data transfers between the IDPs and the main memory. PID-Join overcomes the challenges by prototyping and evaluating hash, sort-merge, and nested-loop algorithms optimized for the IDPs, enabling fast inter-IDP communication using host CPU cache streaming and vector instructions, and facilitating fast rank-wise data transfers between the IDPs and the main memory. Our evaluation using a real system equipped with eight UPMEM DIMMs and 1,024 IDPs shows that PID-Join greatly improves the performance of in-memory join over various CPU-based in-memory join algorithms.

Polling-Based Memory Interface

Non-volatile memory has been extensively researched as the alternative for a DRAM-based system; however, the traditional memory controller cannot efficiently track and schedule operations for all the memory devices in heterogeneous systems due to different timing requirements and complex architecture supports of various memory technologies. To address this issue, we propose a hybrid memory architecture framework called POMI (POlling-based Memory Interface). It uses a small buffer chip inserted on each DIMM (Dual In-line Memory Module) to decouple operation scheduling from the controller to enable the support for diverse memory technologies in the system. Unlike the conventional DRAM-based system, POMI uses a polling-based memory bus protocol for communication and to resolve any bus conflicts between memory modules. The buffer chip on each DIMM will provide feedback information to the main memory controller so that the polling overhead is trivial. We propose two unique designs. The first one adds additional bus lines for sending the feedback information, and the second one utilizes the Command/Address bus. The framework provides several benefits: a technology-independent memory system, higher parallelism, and better scalability. Our experimental results show that POMI can efficiently support both homogeneous and heterogeneous systems. Compared with the conventional DDR4-2400 implementation, our scheme improves the performance of memory-intensive workloads by 3.7% on average. Compared with an existing interface for hybrid memory systems, Twin-Load, it also improves performance by 22.0% on average for memory-intensive workloads.

A review on Buffer Chips and growing Memory Bandwidths

Abstract: The rapid development of CPU technology and the increase in the number of functionalities involved in a chip demand improvement in the memory bandwidth to feed data to the growing pipeline technology. Slower memory bandwidth would result in reduced CPU utilization and make the processor stay idle. The rise in memory bandwidth comes with the challenge of maintaining the signal integrity and affects the number of DIMM (Dual Inline Memory Module) slots in a channel and reduces memory capacity. The challenge of maintaining the signal integrity with the increase in the frequency of operation is solved by introducing additional interfacing chips between the memory controller or CPU and memory module. Buffer chips are used in servers to maintain signal integrity and meet the timing parameters for the commands and addresses sent to the memory modules. Buffer chips help in increasing the frequency of operations as well as the number of memory modules connected. Register Clock Driver (RCD) is one buffer chip used between the memory controller and DRAM that supports the bandwidth and capacity needed in the next-generation data centres. This paper aims at reviewing importance of buffer chips and their application in modern day data centres.

DSIM: Distributed Sequence Matching on Near-DRAM Accelerator for Genome Assembly

Matching nucleic acid sequences has long become the performance bottleneck in genome assembly which aims to connect enormous partial genome reads without prior knowledge of the reference sequence. The intensive and random data accesses of querying sequences using the widely adopted FM-Index data structure have caused in-efficient usage and long runtime of the memory system. Existing software FM-Index tools are limited on algorithmic inefficiency and poor processing parallelism. Solutions on GPU, FPGA and ASIC focus mainly on computational acceleration while still bottlenecked at the memory-bound nature of querying FM-Index. This paper proposes DSIM, a scalable FM-Index querying on near-DRAM accelerators. DSIM supports highly parallel multi-step query processing by distributing partial FM-Index table to different DRAM chips. Each genome sequence is partitioned into shorter queries and dispatched to the corresponding DRAM chip for string lookup. The optimized data layout and execution control on DRAM enables high row-data reuse and minimizes CPU-DRAM data transfers. The light-weight mapping scheme on the host CPU facilitates effective query distribution to DRAM chips and further supports scalability to multiple DIMMs (Dual-Inline Memory Modules). An in-DRAM arbiter is implemented to control the intra-chip data processing without affecting the external memory controller and DDR protocol. Experiments on 128-chip DRAM system showed that DSIM achieves up to 231 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> and 8.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> overall speedup compared to the software FM-Index tool and the state-of-the-art near-DRAM solution respectively.

Simplified and Detailed Analysis of Data Center Particulate Contamination at Server and Room Level Using Computational Fluid Dynamics

Abstract Continuous rise in cloud computing and other web-based services propelled the data center proliferation seen over the past decade. Traditional data centers use vapor-compression-based cooling units that not only reduce energy efficiency but also increase operational and initial investment costs due to involved redundancies. Free air cooling and airside economization can substantially reduce the information technology equipment (ITE) cooling power consumption, which accounts for approximately 40% of energy consumption for a typical air-cooled data center. However, this cooling approach entails an inherent risk of exposing the ITE to harmful ultrafine particulate contaminants, thus, potentially reducing the equipment and component reliability. The present investigation attempts to quantify the effects of particulate contamination inside the data center equipment and ITE room using computational fluid dynamics (CFD). An analysis of the boundary conditions to be used was done by detailed modeling of ITE and the data center white space. Both two-dimensional and three-dimensional simulations were done for detailed analysis of particle transport within the server enclosure. An analysis of the effect of the primary pressure loss obstructions like heat sinks and dual inline memory modules inside the server was done to visualize the localized particle concentrations within the server. A room-level simulation was then conducted to identify the most vulnerable locations of particle concentration within the data center space. The results show that parameters such as higher velocities, heat sink cutouts, and higher aspect ratio features within the server tend to increase the particle concentration inside the servers.

Exploring Efficient Architectures on Remote In-Memory NVM over RDMA

Efficiently accessing remote file data remains a challenging problem for data processing systems. Development of technologies in non-volatile dual in-line memory modules (NVDIMMs), in-memory file systems, and RDMA networks provide new opportunities towards solving the problem of remote data access. A general understanding about NVDIMMs, such as Intel Optane DC Persistent Memory (DCPM), is that they expand main memory capacity with a cost of multiple times lower performance than DRAM. With an in-depth exploration presented in this paper, however, we show an interesting finding that the potential of NVDIMMs for high-performance, remote in-memory accesses can be revealed through careful design. We explore multiple architectural structures for accessing remote NVDIMMs in a real system using Optane DCPM, and compare the performance of various structures. Experiments are conducted to show significant performance gaps among different ways of using NVDIMMs as memory address space accessible through RDMA interface. Furthermore, we design and implement a prototype of user-level, in-memory file system, RIMFS, in the device DAX mode on Optane DCPM. By comparing against the DAX-supported Linux file system, Ext4-DAX, we show that the performance of remote reads on RIMFS over RDMA is 11.44 higher than that on a remote Ext4-DAX on average. The experimental results also show that the performance of remote accesses on RIMFS is maintained on a heavily loaded data server with CPU utilization as high as 90%, while the performance of remote reads on Ext4-DAX is significantly reduced by 49.3%, and the performance of local reads on Ext4-DAX is even more significantly reduced by 90.1%. The performance comparisons of writes exhibit the same trends.

UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory

During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.

A Comparative Study of Energy Savings in a Liquid-Cooled Server by Dynamic Control of Coolant Flow Rate at Server Level

Data center proliferation has been increasing significantly around the world attributed to growth in technologies such as the Internet of Things (IoT), bitcoin mining, and high-performance computing (HPC). A direct consequence of these developments is an enhancement in processing units and a corresponding rise in CPU and GPU power densities. Limitations of air cooling to dissipate increasing power densities in processors have compelled the researchers to move toward better and efficient liquid cooling solutions. In an earlier study, a custom-made mini-rack with liquid-cooled 2OU (open rack Unit) web servers were tested for comparison of centralized and distributed pumping with constant flow rates at the server level. The effect of higher inlet temperature in terms of IT power, cooling power consumption, and CPU temperature was reported along with a comparison of centralized versus distributed pumping. In this article, the same 2OU server is used to show the effect of variable flow rate on server thermal performance. The parameters monitored for performance quantification are the core temperatures, dual in-line memory modules (DIMM) temperatures, and platform controller hub (PCH) temperature. These parameters were reported by varying the CPU power consumption, coolant inlet temperatures, and coolant flow rates by controlling the distributed pumps. The server was fully enclosed with no outside air intake where the CPUs were cooled by cold plates and the rest of the components with internally recirculating air. The results obtained from the experiments were compared with the results obtained from a previous study where the effect of the variable flow rate was ignored. A full-factorial design of experiments (DoE) was designed using Minitab 19 to analyze the results statistically.

Fault Tree Analysis To Understand And Improve Reliability Of Memory Modules Used In Data Center Server Racks

This research focuses on understanding the reliability of an important component of data servers and cloud computing, namely, Dual Data Rate (DDR4) devices in a Dual In-line Memory Module (DIMM) format. Data centres have thousands of DIMMs installed causing large failure rate. A failure to any component of these DDR4 DIMMs can cause operating issues for servers. A DIMM is a Printed Circuit Board Assembly (PCBA) with DDR4 devices that are surface mounted along with resistors, capacitors, a register, and an EEPROM chip. A literature review has shown that Fault Tree Analysis (FTA) does not appear to have been utilized to analyse DIMM failures. As such, this paper proposes an FTA methodology for use in DDR4 DIMM failure analysis. In an effort to validate this methodology, it is demonstrated by Fault Tress developed for three major failure modes observed. For identifying the root causes for these failure modes, various testing tools and techniques have been utilized to perform Root Cause Analysis (RCA) on 809 DDR4 DIMMS. Based on these RCA data, qualitative and quantitative analyses have been performed. Though this RCA/FTA approach is utilized to analyse memory modules found in data centres, the approach can be applied to analyse and predict failures and defect causes for highly automated manufacturing systems.

NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices

To mitigate the impact of non-deterministic media access latencies in new memory technology devices, a recently proposed Non-Volatile Dual In-line Memory Module (NVDIMM) standard, NVDIMM-P uses novel out-of-order transaction commands. The previous DRAM simulators are unable to support this transaction protocol due to deterministic DDR timing. Also, existing NVDIMM simulators are customized for NAND flash memory, which are not generally applicable to emerging Non-Volatile Memory (NVM). In this letter, we present NMTSim, a transaction-command based and cycle accurate simulator for new memory technology devices. Strictly conforming to NVDIMM-P standard, NMTSim introduces a new memory controller with transaction handling and command issuing capabilities. To enable simulation for emerging NVM using DDR4 standard, we propose some new NVM timing parameters and incorporated them into DRAMSim2. Furthermore, DRAMSim2 is augmented with transaction handling and command scheduling logic to be the backend for the media controller. In addition, NMTSim incorporates an optimized transaction command issuing policy and an early notification mode to optimize access latency. We verify NMTSim using Intel Optane and characterize its performance using synthetic benchmarks with different read / write ratios.

THz Channel Characterization of Chip-to-Chip Communication in Desktop Size Metal Enclosure

This article presents characterization of terahertz (THz) wireless channel inside a desktop size metal enclosure with the consideration of several different scenarios. Measurements indicate that both traveling wave and resonating modes exist inside the metal enclosure. Measurements for line-of-sight (LoS) propagation inside the empty metal enclosure show that the path loss significantly changes as a function of the transceiver’s height. It is found that this variation is due the resonant modes, contribution to the received power. Reflected-non-LoS (RNLoS) measurements show that for the same distance, the difference between the mean path loss measured inside the metal box and in a free space is limited to 1 dB, with traveling wave dominating the channel. This indicates that reflectors can be used as wave-guiding objects in metal enclosures. Finally, obstructed-LoS (OLoS) path loss measurements with the parallel dual in-line memory modules (DIMMs) as obstructions show the constructive/destructive effect on the waves due to multipath introduced by the parallel-plate structures. Compared to the free space scenarios, multipath is introduced by the traveling wave bouncing back and forth between the transceiver sides of the cavity, which introduces stronger fluctuations in observed pathloss and reduces the coherence bandwidth of the channel.

A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems

Dynamic random access memory (DRAM) reliability has become one of the critical issues in embedded systems, as DRAM process technology advances with the increase in bit error probability. Unfortunately, redundant error-correction code (ECC) chips cannot be applied to embedded systems since cores and DRAMs are tightly coupled without a dual in-line memory module (DIMM) slot to account for the form factor, cost, and limited pin count. Therefore, ECC parities are typically placed in the same physical array where the user and system data reside. This coexistence eventually deteriorates data locality, which could be the critical factor in DRAM performance degradation. To address this issue, we propose an ECC scheme called locality-aware compression (LoComp) which integrates a compression algorithm, DRAM data layout, and memory controller especially optimized for embedded systems. We focus on the locality of the dataset and its corresponding metadata, as well as spatial data locality in the design of DRAM data layout, which reduces the number of row activations. The major feature in a compression algorithm is adjusting the misalignment of data streams caused by the data packing in many embedded systems. Moreover, we specialize the memory controller to reduce DRAM access for ECC parities and compression flags. The core technologies for the memory controller are the adoption of a set of small caches for metadata and the support of partial write operation without changing the DRAM interface. LoComp+, an enhanced version of LoComp, further reduces DRAM access for metadata by placing the metadata close to the corresponding data. In the experiment, previous works increase the DRAM access time from 68% to over twice the value compared to ECC DIMM. Whereas, LoComp and LoComp+ show reduced performance degradation by 33% and 48%, respectively. In other words, LoComp and LoComp+ substantially improved performance from between 13% and 33% compared to previous embedded ECC schemes.

Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface

A parallel branching synchronous dynamic random access memory (SDRAM) channel with write-direction impedance matching (parallel branching with write-direction impedance matching (PBIM)) is proposed for an 8-drop 6.4-Gb/s SDRAM interface. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of two dual in-line memory modules for a 4-drop configuration and the data (data pin) channel uses two kinds of transmission lines with characteristic impedances of 50 and 25 Ω and a resistor on the motherboard. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gb/s in both write and read directions by using the same motherboard area as that of the stub series terminated logic channel and a bit-error-rate tester for transmitter and receiver.

Subsystem under 3D-Storage Class Memory on a chip

In this paper, we propose a subsystem architecture under 3D-Storage Class Memory (3D-SCM), termed SuS, to solve the memory and power wall problems. Placing the processing unit under the 3D-SCM achieves high performance. We evaluate SuS using gem5 and the GPGPU-Sim simulator. The simulation results for the central processing unit (CPU)-based SuS architecture reveal a 100% performance improvement and a 73% energy reduction compared to the CPU architecture using dual in-line memory modules and a 4% performance improvement with a 27% energy reduction compared to the CPU architecture using hybrid memory cube. Moreover, the graphics processing unit (GPU)-based SuS architecture simulation results on the neural network benchmark demonstrate performance improvements of 17% and 7% compared to GPU architectures with graphics double data rate series memory and high bandwidth memory, respectively.

Approximating Beyond the Processor: Exploring Full-System Energy-Accuracy Tradeoffs in a Smart Camera System

The intrinsic error resilience exhibited by emerging application domains enables new avenues for energy optimization of computing systems, namely, the introduction of a small amount of approximations during system operation in exchange for substantial energy savings. Prior work in the area of approximate computing has focused on individual subsystems of a computing system, for example, the computational subsystem or the memory subsystem. Since they focus only on individual subsystems, these techniques are unable to exploit the large energy-saving opportunities that stem from adopting a full-system perspective and approximating multiple subsystems of a computing platform simultaneously in a coordinated manner. This paper proposes a systematic methodology to perform joint approximations across different subsystems, leading to significant energy benefits compared to approximating individual subsystems in isolation. We use the example of a smart camera system that executes various computer vision and image processing applications to illustrate how the sensing, memory, processing, and communication subsystems can all be approximated synergistically. We demonstrate our proposed methodology using two variants of a smart camera system: 1) a compute-intensive smart camera system, $\texttt {AxSYS}_{\texttt {comp}}$ , where the error-resilient application executes locally within the camera and produces the final application output, and 2) a communication-intensive smart camera system, $\texttt {AxSYS}_{\texttt {comp}}$ , that sends the captured image to a remote cloud server, where the error-resilient application is executed and the final output is generated. We have implemented such an approximate smart camera system using an Altera Stratix IV GX FPGA development board, a Terasic TRDB-D5M 5-Megapixel camera module, a Terasic RFS WiFi module, and a 1-GB DDR3 dynamic random access memory small outline dual in-line memory module (SODIMM). Experimental results obtained using six application benchmarks demonstrate significant energy savings (around $7.5\times $ for $\texttt {AxSYS}_{\texttt {comp}}$ and $4\times $ on average for $\texttt {AxSYS}_{\texttt {comp}}$ ) for minimal ( $3.5\times $ – $5.5\times $ (in the case of $\texttt {AxSYS}_{\texttt {comp}}$ ) and $1.8\times $ – $3.7\times $ (in the case of $\texttt {AxSYS}_{\texttt {comm}}$ ) on average for a minimal (<1%) application-level quality loss.

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

In the big data era, data-intensive applications have growing demand for the capacity of DRAM main memory, but the frequent DRAM refresh, high leakage power, and high unit cost bring serious design issues on scaling up DRAM capacity. To address this issue, a nonvolatile dual inline memory module (NVDIMM), which is a hybrid memory module, becomes a possible alternative to replace the DRAM as main memory in some data-intensive applications. The NVDIMM that consists of a small-sized high-speed DRAM and a large-sized low-cost nonvolatile memory (i.e., flash memory) has the serious performance issue on accessing data stored in the flash memory because of the huge performance gap between the DRAM and the flash memory. However, there is limited room to adopt a complex caching algorithm for using the DRAM as the cache of flash memory in the NVDIMM main memory, because a complex caching algorithm itself would already cause too much performance degradation on handling each request to access the NVDIMM main memory. In this paper, we present a lightweight caching algorithm to boost NVDIMM performance by minimizing the cache management overhead and reducing the frequencies to access flash memory. A series of experiments was conducted based on popular benchmarks, and the results demonstrate that the proposed algorithm can effectively improve the performance of the NVDIMM main memory.

Measurements of Thermally-Induced Curvatures and Warpages of Printed Circuit Board during a Solder Reflow Process Using Strain Gauges

Measurements of the curvatures and warpages of a printed circuit board (PCB) during a thermal solder reflow process using strain gauges are proposed in this study. In the experiments, a shadow moiré is used for measuring the out-of-plane deformations (or warpage) of a bi-material plate and a PCB with dual in-line memory module (DIMM) sockets during solder reflow heating, while the finite element method (FEM) is used to analyze the thermally-induced deformation of the PCB specimen for ensuring the validity of the measurement. Conventional strain gauges are employed to measure the strains (albeit as in-plane strain data) in both specimens during the solder reflow process. The results indicate that the strain gauge-measured strain data from the top and bottom surfaces of both specimens during the solder reflow can be converted into curvature data with specific equations, and even into global out-of-plane deformations or warpages with a proposed simple beam model. Such results are also consistent with those from the shadow moiré and FEM. Therefore, it has been proved that the strain gauge measurement associated with the simple beam model can provide a method for the real-time monitoring of PCB deformations or warpages with different temperatures during the solder reflow process.

An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems

As dynamic random access memories (DRAMs) operate in the field, hard errors resulting from wearout occur. Unless corrected or repaired, hard errors halt normal operations, degrading the performance of a system and causing the replacement of memory modules. To improve performance and availability of memory modules, error-correcting codes (ECCs) are employed in a memory system. However, since recent field studies on DRAM errors have shown that a correctable error is highly likely to result in another error with the same address and in the same column or row, incorporating ECCs for mitigating not only soft errors but also hard errors in field operations is insufficient for ensuring reliable field operations. We propose a methodology that detects and repairs aging errors in DRAMs while operating in the field. We propose a methodology that reconfigures the remaining redundant resources after manufacturing-level repair into postpackage redundant resources. We also propose an ECC-assisted postpackage repair (PPR) flow that detects an error, identifies the type and location of the error, and invokes PPR for aging errors without built-in self-test/repair circuits. Employing a 2-GB ECC–dual in-line memory module of data-rate type three synchronous dynamic random access memories as a case study, we demonstrate that our PPR scheme improves the lifetime of DRAMs.