Dual-gate High Electron Mobility Research Articles

35 nm InAlAs/InGaAs Based Single Gate and Dual Gate High Electron Mobility Transistor: A Comparison

35 nm InAlAs/InGaAs Based Single Gate and Dual Gate High Electron Mobility Transistor: A Comparison

A high-gain high-power amplifier MMIC for V-band applications using 100 nm AlGaN/GaN dual-gate HEMTs

In this paper we present the design and realization of a high-power amplifier in grounded coplanar transmission line technology using AlGaN/GaN dual-gate High electron mobility transistors (HEMTs) with a gate-length of 100 nm to achieve a high gain per stage and high output power. A large-signal model was extracted for the dual-gate HEMT based on the state-space approach. For the fabricated dual-stage amplifier a continuous-wave saturatedoutput power of up to 24.8 dBm (0.84 W/mm) was measured at 63 GHz for 20 V drain bias. A small-signal gain of more than 20 dB was achieved between 56 and 65 GHz.

Linearity Study on Enhance/Depletion Dual-Gate High Electron Mobility Transitors using Gain Mapping Method

Power gain linearity was studied using gain mapping method for enhance/depletion (E/D) dual-gate high electron mobility transistors (HEMTs). This method contains next steps; S-parameter and drain current were measured for all drain and gate voltage where interested. Maximum stable gain (MSG), maximum available gain (MAG) and H21 parameters were then calculated for frequency which is interested. These parameters were plotted on drain-current and drain voltage plane. By using this method into dual-gate HEMTs, it was found that threshold voltage of the second gates are essential for gain linearity and have its optimum value.

A novel dual-gate high electron mobility transistor using a split-gate structure

The split-gate concept has been applied to dual-gate high electron mobility structures for room-temperature operation. The gates are configured so that the second gate is in close proximity to the gap defined by the split-gate electrodes. This allows both gates to control the carrier density in the same region of the device, so that it is possible to control the threshold voltage for either gate by altering the bias at which the other gate is held. The effect of changing the gate configuration is demonstrated.