Dual Damascene Copper Interconnects Research Articles

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this paper, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First, we show that multisegment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: 1) reservoir-enhanced acceleration; 2) sink-enhanced acceleration; and 3) a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this paper since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. The simulation results show that using the proposed method, we can reduce the EM lifetime of a chip from ten years down to a few hours (about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> × acceleration) under the 150 °C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs.

Experimenting and modeling of catastrophic failure in electromigration-induced resistance degradation for deep submicron dual-damascene copper interconnects

The features of electromigration-induced resistance change profile are important aspects of reliability, especially for ULSI interconnect. By experimenting on 0.28 µm wide Cu dual-damascene interconnects, clear evidence of catastrophic failure is observed even when the failure criterion of only 2% resistance change is imposed. Applying theoretical constitutive law of degradation and using basic principles of generic model, constitutive equation for resistance degradation in electromigration is derived and simulated for catastrophic failure. Then real-time resistance change profile is obtained by a simple analytical model which incorporates the Nernst-Einstein relation of mass transport. The convergence of the analytical model to the generic one is also shown. The various aspects of catastrophic failure are discussed. A good correlation between the results obtained from the model and experiment are shown.

Effect of layout on electromigration characteristics in copper dual damascene interconnects

This study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10μm used for 40nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063μm. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40nm or below technology.

X-ray Characterization of PEALD versus PVD Tantalum Nitride Barrier Deposition and the Impact on Via Contact Resistance

Plasma enhanced atomic layer deposition (PEALD) of TaN demonstrated the significant benefit of lowering via resistance in back-end-of-line (BEOL) dual damascene copper interconnects with a line width of 32 nm, although PEALD TaN possessed a much higher intrinsic resistivity, approximately 2000 μΩcm, compared to physical vapor deposition (PVD) of Ta-rich TaN with a value around 250 μΩcm. The mechanism of lowering via resistance was studied by X-ray characterization techniques such as X-ray fluorescence (XRF) and X-ray reflectivity (XRR). XRF analysis indicated the nucleation rate of PEALD TaN is higher on a metal surface compared to a dielectric surface. XRR analysis revealed a smoother and damage free surface between PEALD TaN and silicon oxide, while a rougher interface was formed between PVD TaN and silicon oxide. Via resistance reduction with PEALD TaN is suggested to be related to reduced physical damage at the via bottom.

56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme

In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level. Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window has been demonstrated, showing no impact on RC performance. The introduction of a self-aligned via (SAV) process with a TiN hard-mask is able to provide a robust process window in terms of via-metal short yield at line and via level. SAV implementation at these dimensions also affects the aspect-ratio of the structures and leads to new challenges in metallization: optimized profile, without bowing or undercut, is mandatory to enable the filling of 28nm lines. The metal hard-mask has to be removed or at least faceted by erosion. This can be achieved by conventional RIE process optimization, but pushes the RIE selectivity to challenging limits. Physical dimensions on target and via chain yield have been demonstrated by fine tuning RIE process. Profile improvement can also be achieved by the introduction of new WET process, helping the removal of the metal hard-mask while being neutral to the ULK. We have demonstrated good yield and reliability with an integration using hard-mask wet removal.

Reduction of annealed-induced wafer defects in dual-damascene copper interconnects

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanical stress in passivated interconnect lines. These mechanisms play a collective role for intensive research of thermal stability for Cu interconnects reliability in CMOS technologies. This paper presents capabilities and performance on samples annealed using furnace vs He in situ anneal and in-line technique developed to reduce total defect count.

Modeling Electromigration Lifetimes of Copper Interconnects

A model for early failure due to electromigration in copper dual-damascene interconnects is proposed. The model is based on analytical expressions obtained from solutions of electromigration stress build-up assuming slit void growth under the interconnect vias. It is demonstrated that the model satisfactorily describes the complex physics of void nucleation and growth of the electromigration damage. Furthermore, it is shown that the simulation results provide reasonable estimates for early electromigration failures.

A compact model for early electromigration failures of copper dual-damascene interconnects

A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.

Finite element modeling of hydrostatic stress distribution in copper dual-damascene interconnects

Hydrostatic stresses of copper dual-damascene interconnects are calculated by a commercial finite element software in this paper. The analytical work is performed to examine the effects of different low-k (k is permittivity) dielectrics, barrier layer and aspect ratio of via on hydrostatic stress distribution in the copper interconnects. The results of calculation indicate that the hydrostatic stresses are highly non-uniform throughout the copper interconnects and the highest tensile hydrostatic stress exists on the top interface of lower level interconnect near via. Both the high coefficient of thermal expansion and the low elastic modulus of the low-k dielectrics and barrier layer can decrease the highest hydrostatic stress on the top interface, which can improve the reliability of the copper interconnects.

The effect of stress migration on electromigration in dual damascene copper interconnects

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to stress migration (SM) and electromigration (EM). At use condition, these two failure mechanisms play a collective role in causing interconnect failure. We present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal, where the EM median-time-to-failure (t50) for the majority of samples could be degraded by 30%–60%. For the upper metal of Cu interconnects, the t50 is degraded by about 10%. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. It is proposed that SM can influence EM when there is significant amount of vacancy accumulation due to SM in the cathode area which accelerates EM nucleation time. In the case of the MX structure, our experimental results show that SM and EM interaction occurs exactly below the via at the MX cathode side, leading to abrupt failures. On the other hand, in MX+1 structure, vacancies are likely to accumulate at the edge of upper metal lead during SM test, thus accelerating the failure during subsequent EM test. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms.

Effect of Electron Flow Direction and Via Number on Electromigration Mechanism for Copper Dual Damascene Interconnects

In this study, the effects of the via number and the current direction on electromigration characteristics in the dual-damascene Cu lines have been investigated. The results reveal an interesting difference in electromigration behavior of electron up- and down-flow directions on the multi-via structures. Increasing the via number results in a higher electromigration failure time and then reaches saturation for electron up-flow case. As for electron down-flow direction, the failure time is independent of the via number. Moreover, the failure time of Cu lines with via structure is lower than that without via structure. A higher current density at the triple junction site in the inner via is the possible mechanism, resulting in a shorter failure time and via-number independent. These observed effects are specific to Cu dual-damascene structures and can provide great technological implications in electromigration improvement.

Moisture effect on electromigration characteristics for copper dual damascene interconnection

The influence of moisture on Cu line electromigration (EM) behavior of dual damascene interconnection is reported. The authors have found that moisture has a negative influence on EM behavior, but it depends on the seal-ring structure located along the peripheral of the test pattern. The reduced Cu lifetime, observed for tested samples without seal-ring structure, was due to lateral moisture penetration. Lateral moisture diffusion was considered an effective mechanism for deteriorating the Cu interface during the die-sawing processing for structures without seal-ring layout. As a result, the seal-ring layout is effective and essential in Cu/low-dielectric (low-k) material integrity to prevent moisture penetration during the package procedures.

Helium Ion Secondary Electron Mode Microscopy For Interconnect Material Imaging

The recently developed helium ion microscope (HIM) is now capable of 0.35 nm secondary electron (SE) mode image resolution. When low-k dielectrics or copper interconnects in ultra large scale integrated circuits (ULSI) interconnect structures were imaged in this mode, it was found that unique pattern dimension and fidelity information at sub-nanometer resolution was available for the first time. This paper will discuss the helium ion microscope architecture and the SE imaging techniques that make the HIM observation method of particular value to the low-k dielectric and dual damascene copper interconnect technologies.

Electromigration in width transition copper interconnect

Electromigration (EM) experiments are conducted for submicron dual damascene copper interconnects with width transition. The direction of electron flow (from narrow-to-wide segment and wide-to-narrow segment) and the ratio of lengths (e.g. ratio of narrow-to-wide segment lengths) are found to be significant factors in determining the life-time of such interconnects. About 69% shorter EM life-time is obtained for the case of electron flow from narrow-to-wide segment, and thus to avoid over estimation of EM life-time of such interconnect system, the direction of the electron flow should be chosen appropriately in the reliability assessment. On the other hand, it is found that the width transition location is not the failure site, and finite element model is presented to explain the experimental findings.

Electromigration Induced Metal Voiding Mechanism on Electron Directions and Via Numbers Effect for Copper Dual Damascene Interconnection

not Available.

Moisture Effect on Electromigration Characteristics for Copper Dual Damascene Interconnection

not Available.

Very high current density package level electromigration test for copper interconnects

In this paper, we present quantitative analyses of the impact of Joule heating on the package level electromigration (EM) test of copper dual damascene (DD) interconnects with linewidths of 0.28 and 0.7 μm. A total of 120 samples are tested with a maximum current density of 8 MA/cm2. It is found that high test current density has a negligible impact on the estimation of activation energy and offers an opportunity to shorten the test time. However, the current density exponent is found to be a strong function of test current density, especially for interconnects with a larger linewidth. Correction due to Joule heating on the estimation of the current density exponent is described.

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

Copper dual-damascene (DD) interconnects are fabricated with low-k organic film (SiLKtrade) without any etch-stop layers by use of dual hard mask (dHM) process combined with sidewall-hardening etching step. It is a key point to reduce shoulder loss during trench etching at connecting regions of vias and trenches, so that hardening of the via-sidewall by fluorocarbon plasma during via etching is implemented. Careful designs of dual hard mask structures and their patterning sequence are carried out for the process without etch-stop layer under the trench. The two-layered interconnect with low-k structure has achieved low via-resistance of 0.65 Omega at 0.28 mumOslash with keeping large tolerance of misalignment up to 0.1 mum.

Effect of Layout Variation on Stress Migration in Dual Damascene Copper Interconnects

The effect of layout variation on stress migration (SM) in Cu damascene interconnects was investigated in detail. In an extrusion pattern in which narrow lines are connected to a wide line, the failure rate decreases as the narrow line becomes longer and wider. It was found that there is a maximum failure rate between 150 and 200 °C for all test patterns. The results for the SM failure rate showed that the initial rate of increase of SM failure for the extrusion pattern is much larger than that for the conventional wide pattern. The effect of the narrow linewidth on the SM failure rate cannot be understood by considering the previous diffusion mechanism. Based on these results, the dependence of vacancy diffusion path and SM failure mechanism on the layout variation is discussed.

Effect of strains on anisotropic material transport in copper interconnect structures under electromigration stress

We analyzed the effect of strains on material transport in a typical dual damascene copper interconnect via under electromigration stress. The electromigration model incorporates all important driving forces for atom migration coupled with the solution of the electrical and thermal problems. Our approach differs from others by considering a diffusivity tensor in the transport equation taking into account the diffusion anisotropy generated by the applied strains. We have obtained off-diagonal components of the diffusivity tensor up to 30% of the diagonal ones and a different distribution of vacancies due to electromigration.