Dual-core Platform Research Articles

Thermo-Induced Coalescence of Dual Cores in Double Emulsions for Single-Cell RT-PCR

Single-cell reverse-transcription polymerase chain reaction (RT-PCR) has shown significant promise for transcriptional profiling of heterogeneous cells. However, currently developed microfluidic droplet-based methodologies for single-cell RT-PCR often require complex chip design to accommodate the associated multistep processes as well as customized detection platforms for high-throughput analysis. Herein, we proposed a dual-core double emulsion (DE)-based method to streamline the single-cell RT-PCR through thermo-induced coalescence of the dual cores. The dual-core DEs were produced by pairing two water-in-oil single emulsions containing a single-cell/lysis buffer and RT-PCR mix, respectively. After complete lysis of single cells in one of the cores, the dual-core DEs were merged by gentle heating, made possible by the optimized glycerol concentration present in the cores. Upon the coalescence of dual cores, the alkaline lysis buffer present in the core of the cell lysate was neutralized by the reaction buffer presented in the RT-PCR core, allowing TaqMan assay-based RT-PCR to occur effectively within the DEs. To demonstrate the potential of this streamlined dual-core platform, AKR1B10-positive A549 cells and AKR1B10-negative HEK293 cells were investigated via the TaqMan assay. Subsequently, specific transcript of AKR1B10 was readily available for quantitative profiling at the single-cell level using a commercially available flow cytometer in a high-throughput manner.

Information Processing Based on SQLite for Target Tracking System

As for the digital visual surveillance system, the traditional database and hardware platform can not be good at processing vast quantities of information. Combined with ActiveX Data Objects (ADO) technology, the information processing system was built by using SQLite database with embedded dual-core platform. The embedded database SQLite is implanted in the existing embedded hardware platform DM6446. And processing modules and operating interface were designed based on SQLite and the embedded hardware platform. The designed system can play a role as the core of data processing. The experiments show that the system can meet the requirements of the visual information processing such as data mining, online system analysis, data post-processing and so on.

Advanced SIMD를 이용한 화면 간 예측 고속화방법

본 논문에서는 ARM Cortex-A9 듀얼코어 플랫폼에서 지원하는 병렬처리 기법 중 하나인 Advanced SIMD기반의 NEON을 적용한 H.264/AVC 고속화 움직임추정 방법론을 연구하였다. 다양한 움직임추정 방법 중 하나인 전역탐색기법에 NEON을 적용하여 각 매크로블록의 SAD 연산횟수를 1/4 감소시켰다. 해당 매크로블록의 픽셀 값들을 8개의 16bit NEON 레지스터에 할당하였고, NEON에서 지원하는 Intrinsic 함수를 사용하여 동시에 128bit 연산을 수행하였다. 이러한 방법으로 계산된 SAD 값들 중 최소 SAD 값을 가지고 정확한 모션벡터를 선정했다. 그 결과 영상의 크기 및 매크로블록의 크기에 따라 성능이 평균 30% 이상 향상되는 효과를 검증하였다. An H.264/AVC fast motion estimation methodology is presented in this paper. Advanced SIMD based NEON which is one of the parallel processing methods is supported under the ARM Cortex-A9 dual-core platform. NEON is applied to a full search technique with one of the various motion estimation methods and SAD operation count of each macroblock is reduced to 1/4. Pixel values of the corresponding macroblock are assigned to eight 16-bit NEON registers and Intrinsic function in NEON architecture carried out 128 bits arithmetic operations at the same time. In this way, the exact motion vector with the minimum SAD value among the calculated SAD values can be designated. Experimental results show that performance gets improved 30% above average in accordance with the size of image and macroblock.

A Vision-Based Driver Nighttime Assistance and Surveillance System Based on Intelligent Image Sensing Techniques and a Heterogamous Dual-Core Embedded System Architecture

This study proposes a vision-based intelligent nighttime driver assistance and surveillance system (VIDASS system) implemented by a set of embedded software components and modules, and integrates these modules to accomplish a component-based system framework on an embedded heterogamous dual-core platform. Therefore, this study develops and implements computer vision and sensing techniques of nighttime vehicle detection, collision warning determination, and traffic event recording. The proposed system processes the road-scene frames in front of the host car captured from CCD sensors mounted on the host vehicle. These vision-based sensing and processing technologies are integrated and implemented on an ARM-DSP heterogamous dual-core embedded platform. Peripheral devices, including image grabbing devices, communication modules, and other in-vehicle control devices, are also integrated to form an in-vehicle-embedded vision-based nighttime driver assistance and surveillance system.

A videotext in picture display system with embedded videotext extraction on a dual-core platform

This research utilizes embedded videotexts to achieve an intelligent multimedia display. We design a videotext in picture (TiP) display system which can extract the videotexts in the subchannel and then combine these videotexts with the main channel. This system was constructed on a dual-core platform to reach real-time videotext extraction and display. A schedulable design framework was proposed to partition the TiP display with videotext extraction in pipeline running. A data-aware transfer scheme was designed in which some data can be reused. Single instruction multiple data (SIMD) based mechanisms were created to enhance the computational efficiency on numerous convolutions and accumulations in videotext extraction. Quadruple buffering was manipulated to process the input/output in videotext extraction simultaneously. To optimize the labeling and filling tasks, the multi-banking and multi-tasking were developed. The evaluation results indicated that the proposed techniques can speed up the processing time of TiP display with videotext extraction. The equivalent comparison presented that the proposed techniques are more proficient at realizing videotext extraction.

Motivation and Implementation of a Software H.264 Real-Time CIF Encoder for Mobile TV Broadcast Applications

An encoding system was implemented purely in software for sending H.264 video multicast to mobile devices. The H.264 encoder is a multi-threaded parallel-GOP encoder. It is capable of running in real-time with an AMD Opteron 1.8 GHz dual-core platform in baseline profile at CIF resolution at 1 Mbps-Real-time video encoding is accomplished with aggressive single instruction multiple data assembly code optimizations and advanced algorithms. A time control algorithm was developed to quell the mode decision process from spending too much time per frame. Transmission of the audio and video streams is on an IP layer over WiFi and DVB-H. DVB-H is chosen for its power saving and reliability features. Using the IP network, the encoder can be repurposed for applications other than mobile broadcast video.

Realization of Embedded Multimedia System Based On Dual-Core Processor OMAP5910

This paper focuses on the realization of a complete embedded system using the dual-core processor OMAP5910. Detailed description of how to compose the hardware system is presented with a description of the software system on our platform. Tasks communication between the two cores is realized using the DSP driver. The system bootloader and the DSP bootloader are described in detail. The implementation of the MPEG-4 video decoder has been realized on the presented system. Higher speed can be achieved and less power is needed for MPEG-4 video processing on the dual-core platform. This dual-core system can be applied to 3G wireless communication, robot control and vision systems.