Dual ARM Cortex-A9 Research Articles

Efficient and high-performance pedestrian detection implementation for intelligent vehicles

Implementing pedestrian detection real-time embedded systems remains a major challenge. Detecting pedestrians in an advanced driver assistance system requires a lot of time and resources. The method based on Multi-Scale Region Covariance Descriptor (MSRCD) and Support Vector Machine (SVM) is one of the most effective approaches to perform pedestrian detection. However, such implementation is difficult to be executed in real time on embedded systems. This paper presents three improvements to adapt the solution based on the MSRCD descriptor and SVM classifier for embedded pedestrian detection. First, a new feature combination capable to provide the most accurate description at a minimum processing time for MSRCD is proposed. Second, to speed up the SVM classification, a new approach that adopts the mean SVM technique and Euclidian distance is proposed. Third, parallel implementation is exploited to accelerate processing time on multi-core architectures. The software implementation is performed using the INRIA data set. 18.94% processing time speed-up, 48.21% less memory usage, and 2.38% improved detection accuracy are achieved using the proposed descriptor. Moreover, 58.22% processing time speed-up is obtained for the proposed classifier while keeping the same testing accuracy. The parallel implementation is performed using dual ARM Cortex-A9 processors of a selected Xilinx zynq platform. The obtained results confirmed the effectiveness of the proposed parallelization at accelerating the computing time about 3 times the original sequential processing.

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems

The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibit errors. NAND flash memory is normally used to store the file system metadata and page mapping information. Thus, a broken physical page containing metadata may cause an unintended and severe change in functionality of the entire flash. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multibit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-chip hierarchy, or hardware implementation of flash memory chip. We evaluate Meta-Cure under a real-embedded platform using a variety of I/O traces. The evaluation platform adopts dual ARM Cortex A9 processor cores with 64 Gb NAND flash memory. We have evaluated the effectiveness of Meta-Cure on the new technology file system file system. Experimental results show that the proposed technique can reduce uncorrectable page errors by 70.38% with less than 7.86% time overhead in comparison with conventional error correction techniques.