DSP Platforms Research Articles

Performance analysis of a bridgeless power factor correction (PFC) buck–boost LED driver with ripple diversion scheme for extended lifespan

SummaryIn the state of the art of AC‐fed light‐emitting diode (LED) drivers, power factor correction (PFC), second harmonic LED current ripple elimination, low current total harmonic distortion (iTHD), removal of electrolytic capacitors (EC) and flicker‐free operation are the major challenging issues. This paper proposes a bridgeless universal voltagerange AC‐fed LED driver that overcome the major issues of LED driver. The bridgeless buck–boost PFC configuration minimizes the losses relative to the front‐end bridge rectifier‐based configurations. Operating in discontinuous conduction mode (DCM), the source current tracks the input voltage shape for a wide operating range, achieves inherent PFC and maintains low input current THD. Also, this provides significant reduction in the output current ripple with the ripple diversion circuit (RDC) connected in shunt across the LED load, which relatively reduces and utilizes low value of output capacitance. Hence, a flicker‐free operation is achieved without the use of electrolytic capacitors. In addition, the elimination of ECs improves the operating lifespan of the proposed LED driver. A detailed theoretical analysis and results of the proposed LED driver are validated on DSP and analog controller platforms with a 62 W/62 V experimental laboratory prototype. The experimental results confirm that the proposed LED driver achieves a power factor of 0.94–0.997, input current THD of maximum 6.8%, output current ripple of 5%, and a peak efficiency of 91.25% for the wide range of input voltage variation. These indices also satisfy IEC‐61000‐3‐2 and IEEE 1789‐2015 standard limits.

Generalized Accurate Harmonic Calculation Method Based on Discretized Double Fourier Series to Solve Double-Pulse Phenomenon

Harmonic issues have always been paid attention to in electrical systems, and accurate calculation of the amplitude and phase of each harmonic has become one of the research focuses of scholars. This article develops a generalized harmonic closed-form analytical solution for a single-phase voltage source inverter (VSI) under digital sinusoidal pulse width modulation (DSPWM) and dead-time effects. This article is the first to point out the double-pulse phenomenon that can occur when using a double Fourier series to solve the harmonic spectrum due to the discontinuity of the dead-time effects and half-cycle integrals. Analysis and data comparison shows that this phenomenon can affect the accuracy of harmonic calculations. An discretized double Fourier series method is proposed to solve this phenomenon. Moreover, the problems of missing pulse caused by the modulation under a specific current phase and current zero-crossing are also solved, improving the harmonic calculation's accuracy and generality. Simulation analysis and the results of inverse fast Fourier transform (IFFT) proved the correctness of the optimization method. And the experimental results are obtained on the DSP and SIC platforms, which are in good agreement with the expression calculation results

IMPROVED METHODOLOGY FOR APPLYING THE OBJECT MODEL OF DSP-SSP SYSTEM INTERACTION THROUGH AD EXCHANGE

In the article analyzed the interaction of DSP-SSP systems through Ad Exchange. According to the results of the analysis, the purpose of scientific research is formed, which is that for automate process of the buying and selling of media content, to carry out simulations and to prove the feasibility of using the implemented platforms on the basis of the advanced method of application of the object model of interaction of DSP-SSP systems. The authors found that Ad Exchange is an intermediary between DSP and SSP platforms and implements the module one to many. Has been identified that this system enables the digital marketplace where publishers and advertisers come together to trade digital inventory. It is concluded that Ad Exchange is a standalone platform that facilitates and simplifies programmatic ads buying. The authors presented the model of the Ad Exchange system, presents advantages and disadvantages are indicated. It is concluded that the Validator block, which advertises only for a specific contingent of people, was first proposed by theauthors as the most important component of this model. The Validator block is the main advantage of the system presented in the article over others. An advanced technique for using an object model of DSP-SSP systems interaction through Ad Exchange is offered. It is determined that an important component for the implementation of this methodology is Analytic, which was implemented on the DSP platform, where the client can keep track of important winnings, clicks and other. By incorporating the Validator block, the well-known DSP and SSP algorithm is improved. Based on the proposed model, a simulation was performed where the Validator block was implemented. It is concluded that Ad Exchange is a tool for automating the process of buying and selling Internet content. This allows you to earn more money and save time on transactions. The recommendations developed by the authors track poor quality proposals and deal with risks.

УДОСКОНАЛЕНА МЕТОДИКА ЗАСТОСУВАННЯ ОБ’ЄКТНОЇ МОДЕЛІ ВЗАЄМОДІЇ DSP-SSP СИСТЕМ ЧЕРЕЗ AD EXCHANGE

In the article analyzed the interaction of DSP-SSP systems through Ad Exchange. According to the results of the analysis, the purpose of scientific research is formed, which is that for automate process of the buying and selling of media content, to carry out simulations and to prove the feasibility of using the implemented platforms on the basis of the advanced method of application of the object model of interaction of DSP-SSP systems. The authors found that Ad Exchange is an intermediary between DSP and SSP platforms and implements the module one to many. Has been identified that this system enables the digital marketplace where publishers and advertisers come together to trade digital inventory. It is concluded that Ad Exchange is a standalone platform that facilitates and simplifies programmatic ads buying. The authors presented the model of the Ad Exchange system, presents advantages and disadvantages are indicated. It is concluded that the Validator block, which advertises only for a specific contingent of people, was first proposed by the authors as the most important component of this model. The Validator block is the main advantage of the system presented in the article over others. An advanced technique for using an object model of DSP-SSP systems interaction through Ad Exchange is offered. It is determined that an important component for the implementation of this methodology is Analytic, which was implemented on the DSP platform, where the client can keep track of important winnings, clicks and othere. By incorporating the Validator block, the well-known DSP and SSP algorithm is improved. Based on the proposed model, a simulation was performed where the Validator block was implemented. It is concluded that Ad Exchange is a tool for automating the process of buying and selling Internet content. This allows you to earn more money and save time on transactions. The recommendations developed by the authors track poor quality proposals and deal with risks

VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing

QR decomposition (QRD) is one of the most widely used numerical linear algebra (NLA) kernels in several signal processing applications. Its implementation has a considerable and an important impact on the system performance. As processor architectures continue to gain ground in the high-performance computing world, QRD algorithms have to be redesigned in order to take advantage of the architectural features on these new processors. However, in some processor architectures like very large instruction word (VLIW), compiler efficiency is not enough to make an effective use of available computational resources. This paper presents an efficient and optimized approach to implement Givens QRD in a low-power platform based on VLIW architecture. To overcome the compiler efficiency limits to parallelize the most of Givens arithmetic operations, we propose a low-level instruction scheme that could maximize the parallelism rate and minimize clock cycles. The key contributions of this work are as follows: (i) New parallel and fast version design of Givens algorithm based on the VLIW features (i.e., instruction-level parallelism (ILP) and data-level parallelism (DLP)) including the cache memory properties. (ii) Efficient data management approach to avoid cache misses and memory bank conflicts. Two DSP platforms C6678 and AK2H12 were used as targets for implementation. The introduced parallel QR implementation method achieves, in average, more than 12[Formula: see text] and 6[Formula: see text] speedups over the standard algorithm version and the optimized QR routine implementations, respectively. Compared to the state of the art, the proposed scheme implementation is at least 3.65 and 2.5 times faster than the recent CPU and DSP implementations, respectively.

Energy Consumption Estimation for Embedded Applications

Energy consumption, indeed, represents one of the essential properties of embedded applications, especially for those devices whose autonomy depends on battery life. The lack of accurate and suitable methodology for energy consumption estimation for embedded applications based on ultra-low power heterogeneous multicore DSP platforms inspired a solution that will be presented in this paper. The solution has been developed as a plugin for the Eclipse based MIDE (Multicore Integrated Development Environment), in order to facilitate production of energy efficient firmware solutions. Evaluation of energy loss has been calculated using instruction-level power analysis, virtual platform, debug information, and diverse input loads. The primary goal was to obtain a precise model of energy consumption that will establish a direct link between program solutions and the amount of energy required for their execution, whilst processing different input loads. Estimation has been validated against empirical data, measured on a real DSP platform. Results show that very high accuracy has been reached.DOI: http://dx.doi.org/10.5755/j01.eie.22.3.15313

Design and Implementation Analysis of OSD based Audio Crosstalk Cancellation with Multi-Channel Inputs on DSP Processors

To overcome the basic system inversion problems in conventional crosstalk cancellation systems, the three channel Optimum Source Distribution (OSD) was developed by Takashi et al., that provides balance between in-phase and out of phase components. The main difficulty in this system is real-time implementation of cross talk cancellation filters on DSP platforms, particularly when filter lengths are very long with system operates on multichannel inputs. This paper discusses the implementation complexities and proposes an efficient approach to reduce the power consumption. It also discusses efficient usage of available processor memory. By utilizing the processor resources and existing frequency domain techniques, this approach would be one of best methods for long filters. The mathematical model, with efficient design for floating point DSP processors, clearly explains the optimization methods at algorithmic and instruction levels. The computational complexity of the proposed method was measured for various multi-channel input sources and the comparison was shown. The results indicate that the proposed method provides efficient computations than existing methods. Keywords: Convolution, Crosstalk Cancellation, Optimal Source Distribution, Overlap Save Method, Uniform Partitioned Convolution

Fingerprint Pre-processing on ARM and DSP Platforms

In minutiae based fingerprint analysis, fingerprint image is pre-processed before extracting features. The pre-processing is carried out to obtain more accurate minutiae points. Implementing fingerprint programs on embedded systems can be considered as important especially for real time standalone applications. Reducing the pre-processing time is important for identification and verification in real time embedded systems. In this study, pre-processing of minutiae based fingerprint system is implemented on two different platforms: Texas Instruments Sitara AM3359 which is a single board computer and OMAP-L138 which is a development kit. OMAP-L138 is a low power application processor based on ARM9 and C674x DSP cores. AM3359 is microprocessor unit based on ARM Cortex-A8 core. Fingerprint pre-processing algorithms are implemented using C/C++ compiler and tested on three different cores: ARM9, DSP and ARM Cortex-A8. The execution times are compared with each other. The results show that using DSP core, execution time is substantially improved. DOI: http://dx.doi.org/10.5755/j01.eee.20.6.7287

Partitioned block frequency domain acoustic echo canceller with fast multiple iterations

Acoustic echo degrades the quality of speech in hands-free telephony. The most popular digital signal processing technique to suppress acoustic echo is adaptive filtering. However, adaptive filtering may require the computational cost optimization in particular when adaptive algorithm is implemented on low-cost DSP platforms. We propose a computationally efficient version of the partitioned block frequency domain adaptive filter with multiple iterations on current data block. The algorithm performs as a cascade of two adaptive filters. The first filter minimizes the Least Square (LS) criteria leading to unbiased estimate of a room response. The second filter speeds up the convergence rate using multiple iterations to minimize modified LS criterion. Coefficients updates calculated in a single step substitute for multiple iterations and decrease computational costs. The complexity of the algorithm is o(log2(R)), where R is a number of iterations. The proposed algorithm was tested in a simulated room and a real reverberant room. Tests proved that our algorithm converges faster compared to algorithms described in literature.

On the Real-Time Hardware Implementation Feasibility of Joint Radio Resource Management Policies for Heterogeneous Wireless Networks

The study and design of Joint Radio Resource Management (JRRM) techniques is a key and challenging aspect in future heterogeneous wireless systems where different Radio Access Technologies (RAT) will physically coexist. In these systems, the total available radio resources need to be used in a coordinated way to guarantee adequate satisfaction levels to all users, and maximize the system revenues. In addition to carry out an efficient use of the available radio resources, JRRM algorithms need to exhibit good computational performance to guarantee their future implementation viability. In this context, this paper proposes novel JRRM techniques based on linear programming techniques, and investigates their computational cost when implemented in DSP platforms commonly used in mobile-based stations. The obtained results demonstrate the feasibility to implement the proposed JRRM algorithms in future heterogeneous wireless systems.

Overcoming the Challenges of Porting OpenCV to TI's Embedded ARM + DSP Platforms

The growing performance and decreasing price of embedded processors are opening many doors, for both developers in the industry and in academia. However, the complexities of these systems can create serious developmental bottlenecks. Sophisticated software packages such as OpenCV can assist in both the functional development and educational aspects of these otherwise complex applications; such tools lend themselves very well to use by the academic community, in particular in providing examples of algorithm implementation. However the task of migrating this software to embedded platforms poses its own challenges. This paper will review how to mitigate some of these issues, including C++ implementation, memory constraints, floating-point support, and opportunities to maximise performance using vendor-optimised libraries and integrated accelerators or co-processors. Finally, we will introduce a new effort by Texas Instruments to optimise vision systems by running OpenCV on the C6000™ digital signal processor architecture. Benchmarks will show the advantage of using the DSP by comparing the performance of a DSP+ARM® system-on-chip (SoC) processor against an ARM-only device.

A real-time implementation of cochlear implant stimulation strategy based on wavelet transform

This paper presents a real-time implementation of the wavelet transform (WT) approach on DSP platforms for a 21-channel cochlear implant (CI) stimulation strategy. DSP platforms provide an effective cost and portable platform for cochlear implant studies. The cochlear implant converts sounds which are received from the outside, into electrical pulses that stimulate nerve endings in the cochlea, in real time. These electrical stimuli are interpreted by the brain as sounds. Different versions of our implementation are examined and compared in terms of processing time speech and accuracy. For real-time experiment, it is crucial that the speech signal be processed with minimal delay from input to output. To achieve this purpose, optimisation techniques have been taken. Thanks to these steps, we have been able to reduce the processing time to approximately 10.5 μs on a 720 MHz TMS320C6416 DSP board. This experiment provides directive guidelines for our work to treat the speech signal sample per sample at real-...

State of the art baseband DSP platforms for Software Defined Radio: A survey

Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.

Multiclass object classification for real-time video surveillance systems

Object classification in video is an important factor for improving the reliability of various automatic applications in video surveillance systems, as well as a fundamental feature for advanced applications, such as scene understanding. Despite extensive research, existing methods exhibit relatively moderate classification accuracy when tested on a large variety of real-world scenarios, or do not obey the real-time constraints of video surveillance systems. Moreover, their performance is further degraded in multi-class classification problems. We explore multi-class object classification for real-time video surveillance systems and propose an approach for classifying objects in both low and high resolution images (human height varies from a few to tens of pixels) in varied real-world scenarios. Firstly, we present several features that jointly leverage the distinction between various classes. Secondly, we provide a feature-selection procedure based on entropy gain, which screens out superfluous features. Experiments, using various classification techniques, were performed on a large and varied database consisting of ∼29,000 object instances extracted from 140 different real-world indoor and outdoor, near-field and far-field scenes having various camera viewpoints, which capture a large variety of object appearances under real-world environmental conditions. The insight raised from the experiments is threefold: the efficiency of our feature set in discriminating between classes, the performance improvement when using the feature selection method, and the high classification accuracy obtained on our real-time system on both DSP (TMS320C6415-6E3, 600 MHz) and PC (Quad Core Intel® Xeon® E5310, 2 × 4 MB Cache, 1.60 GHz, 1066 MHz) platforms.

Trends in multicore DSP platforms

In the last two years, the embedded DSP market has been swept up by the general increase in interest in multicore that has been driven by companies such as Intel and Sun. One reason for this is that there is now a lot of focus on tooling in academia and also a willingness on the part of users to accept new programming paradigms. This industry-wide effort will have an effect on the way multicore DSPs are programmed and perhaps architected. But it is too early to say in what way this will occur. Programming multicore DSPs remains very challenging. The problem of how to take a piece of sequential code and optimally partition it across multiple cores remains unsolved. Hence, there will naturally be a lot of variations in the approaches taken. Equally important is the issue of debugging and visibility. Developing effective and easy-to-use code development and real-time debug tools is tremendously important as the opportunity for bugs goes up significantly when one starts to deal with both time and space. The markets that DSP plays in have unique features in their desire for low power, low cost, and hard real-time processing, with an emphasis on mathematical computation. How well the multicore research being performed presently in academia will address these concerns remains to be seen.

Enhanced Montgomery Multiplication on DSP Architectures for Embedded Public-Key Cryptosystems

Montgomery's algorithm is a popular technique to speed up modular multiplications in public-key cryptosystems. This paper tackles the efficient support of modular exponentiation on inexpensive circuitry for embedded security services and proposes a variant of the finely integrated product scanning (FIPS) algorithm that is targeted to digital signal processors. The general approach improves on the basic FIPS formulation by removing potential inefficiencies and boosts the exploitation of computing resources. The reformulation of the basic FIPS structure results in a general approach that balances computational efficiency and flexibility. Experimental results on commercial DSP platforms confirm both the method's validity and its effectiveness.

A new multi-channel real-time digital signal processing platform for acoustic signal processing and sensor response emulation

In recent years, the DSP group at the University of Manchester has developed a range of DSP platforms for real-time filtering and processing of acoustic signals. A next generation system has now been designed, which incorporates a processor operating at 0.55 Giga MMACS, six input and eight output analogue channels, digital input/output in the form of S/PDIF and a USB interface. The software allows the user, with no knowledge of filter theory or programming, to design and run standard or completely arbitrary FIR, IIR and adaptive filters. Processing tasks may be described and linked using the graphical icon based interface. In addition, the system has the capability to emulate in real-time linear system behaviour such as sensors, instrument bodies, string vibrations, resonant spaces and electrical networks. Tests have confirmed a high degree of fidelity between the behaviour of the physical system and its digitally emulated counterpart. In addition to the supplied software, the user may also program the system using a variety of commercial packages via the JTAG interface.

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidanceof over-constrained synchronization, and its simplified clocking requirements.However, analysis and optimization of self-timed systems under real-time constraintsis challenging due to the complex, irregular dynamics of self-timed operation.In this paper, we review a number of high-level intermediate representationsfor compiling dataflow programs onto self-timed DSP platforms, including representationsfor modeling the placement of interprocessor communication (IPC) operations;separating synchronization from data transfer during IPC; modeling and optimizinglinear orderings of communication operations; performing accurate design spaceexploration under communication resource contention; and exploring alternativeprocessor assignments during the synthesis process. We review the structureof these representations, and discuss efficient techniques that operate onthem to streamline scheduling, communication synthesis, and power managementof multiprocessor DSP implementations.

Low complexity speech coding at 1.2 to 2.4 kbps based on waveform interpolation

Low-rate speech coding technology has recently made a significant progress with the introduction of new interpolative algorithms (Shoham, 1993; Kleijn and Haagen, 1995). The inherent complexity of these algorithms is, however too high too be commercially useful for low-cost applications. In this paper we propose new approaches to low-complexity speech coding at coding rates of 1.2 and 2.4 kbps. The proposed methods utilize all the advantages of interpolatve coding but greatly simplify the analysis and synthesis operations to a point where low-cost two-way digital speech communication can be easily implemented on DSP or host platforms. At 2.4 kbps, the complexity of the proposed coder is about 7.5 and 2.5 MFLOPS for the encoder and decoder, respectively. At 1.2 kbps, the complexity is about 6 and 2.3 MFLOPS for the encoder and decoder, respectively. The small computational load of these coders make them suitable for multi-tasking environment and low-cost terminals. Informal subjective evaluation shows that, at 2.4 kbps, good communication quality is obtained. Communication quality is less than toll quality but the perceived coding effects are not annoying and do not prevent long sustained two-way conversation with high degree of intelligibility. The quality does not significantly degrade at 1.2 kbps and it is considered sufficient for messaging applications.

Configurable logic for digital communications: some signal processing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies.