DSP Module Research Articles

Implementation of FIR Filter and FFT Systems on a STRATIX-III FPGA Processor

In this paper, the implementation of DSP modules like FIR Filter and FFT based systems are designed and implemented. The design is based on high performance FPGA “Cyclone II” and implementation is done after functional and timing simulation. The simulation tool used is ModelSim. The tool for synthesis and implementation is Quartus II. The experimental results shows the functional and timing analysis for all the DSP modules carried out using high performance synthesis software from Altera.

Design and Research of a PMLSM-Driven Elevator Door Machine

Most of the existing elevator door driven by rotary motors, this paper used to design the permanent magnet linear synchronous motor as the Drive Fixed Motor, the door can eliminate the need of drive mechanism between the motor and the door, direct drive door in a straight line, improve reliability and security of the door machine. Through experimental analysis, the design uses DSP and Intelligent Power Module (IPM) combination of control system for elevator door operation by setting curve and stable operation.

The MHD Control System for the FTU Tokamak

In this paper the architecture of the MHD control system for the Frascati Tokamak Upgrade (FTU) is presented. This control is aimed to stabilize tearing modes (TM) in the plasma by EC heating and current drive. TMs are detected and spatially localized by correlating several ECE channels and Mirnov coil signals; two independent antennas are steered in order to track the TM instability. To guarantee short locking time a fast real-time plasma equilibrium code is used to locate the instability when there is no TM evidence and real-time ray tracing code is used to estimate the location where EC power is deposited. A set of hardware consisting of FPGA and DSP modules on PXI bus for executing the diagnosis and control algorithms is proposed. The overall system layout is introduced together with a description of the data communication among the processors.

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

BackgroundLikelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA)-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors.ResultsWe use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10× speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture.ConclusionsHeterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs) [1].

해양용 DGPS 구조개선을 위한 RSIM 설계에 관한 연구

현재 운영되고 있는 해양용 DGPS 시스템은 하드웨어 RSIM 방식으로서 DGPS 구조개선시 고려해야 할 위성항법시스템의 다원화와 미래 해양 사용자의 최소 요구성능을 만족시킬 수 있는 기술 적용에 효율적이지 못하다는 문제가 있다. 본 논문에서는 이러한 문제를 해결하기 위하여 소프트웨어 RSIM 방식으로 해양용 DGPS 시스템을 구조개선하는 방안을 연구한다. 이를 위해 본 논문은 해양용 DGPS 시스템에 적합한 소프트웨어 RSIM 방식을 제안하고, 제안한 방법의 기술적 타당성 분석을 위하여 광대역폭, 높은 표본화 주파수, 데이터 고속전송 사양을 갖는 RF 모듈과 DSP 모듈을 제작하며, 이를 이용하여 제안한 방법을 적용한 해양용 DGPS 시스템을 구현한다. 그리고 신호처리 소요시간 분석을 통하여 개인용 컴퓨터 환경에서 제안한 소프트웨어 RSIM 방식이 실시간으로 운영됨에 문제가 없음을 보인다. 마지막으로 본 논문은 제안한 방법으로 설계된 DGPS 시스템의 보정정보 정확도가 RTCM 221-2006-SC104-STD을 통해 규정된 국제기구 요구성능을 만족시키고 있음을 확인한다. Hardware dedicated off-the-shelf maritime differential GPS RSIM lacks the open architecture to meet all the minimum maritime user requirements and to include future GNSS improvements after recapitalization. This paper carries out a study to replace existing hardware dedicated differential GPS RSIM with software differential GPS RSIM in order to make up the weak point of hardware dedicated off-the-shelf maritime differential GPS RSIM. In this paper, the architecture of software RSIM is proposed for maritime DGPS recapitalization. And the feasibility analysis of the proposed software differential GPS RSIM is performed as the first phase to realize the proposed architecture. For the feasibility analysis, the prototype RF module and DSP module are implemented with properties as wide RF bandwidth, high sampling frequency, and high speed transmission interface. This paper shows that the proposed architecture has the possibility of real time operation of software RSIM functionality onto the PC-based platform through the analysis of computation time. Finally, this paper verifies that the L1/L2 dual frequency software differential RSIM designed according to the proposed method satisfies the performance specifications set out in RTCM paper 221-2006-SC104-STD.

A real time fingerprint identification system based on the AFS8600 sensor and the C6713 DSP processor

AbstractIn this paper, a fingerprint pre‐process and identification algorithm is implemented using the TMS320C6713 DSP starter kit (DSK) module, along with the Authentec AFS 8600 fingerprint sensor. Database: Acquisition is performed using a solid state sensor. The sensor postulates emerge from the theory of the Electric Field technology. Method: Images are first subjected to a frequency and orientation processing. This is achieved using Gabor‐based filters. This processing has been optimized and implemented on the DSP system. A new method has been developed in order to extract the feature vector of the fingerprint image. A grid, centered at the corepoint of the image, is applied to the fingerprint image in order to derive local information. Classification algorithms are developed, which include training as well as evaluating phase. The types of classifiers used were based on the Bayesian approach along with the K‐nearest neighbour. Results: An identification accuracy of 90% was achieved which is comparable to other procedures described in the literature. Conclusion: The combination of a fingerprint processing and identification algorithm using a low cost sensor and DSP module has been presented. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

An efficient RNS parity checker for moduli set {2 n − 1, 2 n + 1, 22n + 1} and its applications

Residue number system (RNS) has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, subtraction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory (CRT) and mixed radix conversion (MRC) for the moduli set {2 n − 1, 2 n + 1, 22n + 1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS.

Implementation and evaluation of a Greek Text To Speech System based on an Harmonic plus Noise Model

The use of text to speech (TTS) systems beyond pure scientific applications has been gaining ground and has been incorporated in everyday life aspects. Thus, the development of TTS system, that can produce synthesized speech of high quality is more than necessary in state-of-the-art everyday life applications. This paper evaluates the performance of a TTS using harmonic plus noise model (HNM) - a speech analysis/synthesis algorithm, as part of its DSP module. A TTS for the Greek language is studied with respect to its DSP module and an evaluation is presented of the HNM algorithm in terms of overall performance and the impact of its attributes on the results quality.

Embedded-based network numerical control technology and system

It is indicated that the general-purposed PC-based numerical control (NC) technology suffers from a number of problems, such as mismatch between system resources and application needs, unsuitability of the operating system to real-time control, lack of self-owned intellectual properties (IP) etc. Further embedded technology is one of the future develop- ment directions of network numerical control. The hardware and software architectures for the embedded-based network numerical control as well as the relevant development and simulation environments are proposed. The hardware structure of the system consists of input and display device, NC unit, PLCs, servo modules, high-speed fieldbuses, and Ethernet etc, all of which are embedded-based. The software system is com- posed of embedded operating system, control and computation components, various other composable modules, design assis- tance system, simulation system etc. The embedded-based NC system can realize all the functions that a general-purposed, PC-based NC system can provide. The development assistance process and auto-generation process for the embedded-based network numerical control software are presented, as well as those for embedded-based PLCs software. A hardware imple- mentation scheme for the embedded-based network numerical control is proposed, and the software architectures of ARM and DSP modules of the central NC unit are introduced. The mostly distinguishing feature of the embedded network numerical con- trol system is that the central numerical control unit is not a general-purposed PC system, but an embedded system instead. The system not only has high computation capacity, flexible structure and low cost, but also is general, combinable, scalable and open.

고정자전류 모니터링에 의한 유도전동기 베어링고장 검출에 관한 연구

이 논문은 다른 종류의 유도전동기 구름베어링 손상을 유도전동기 고정자 전류신호해석을 통하여 검출하고 실시간으로 손상을 진단하는 알고리즘을 개발하였다. 유도전동기 구름베어링의 손상을 검출하기 위하여 정상적인 베어링을 갖는 유도전동기, 축정열에 불량을 가지고 있는 전동기와 베어링 외륜에 구멍을 가지고 있는 2가지 종류의 비정상 베어링을 갖는 유도전동기 3set를 실험시스템을 구축하였다. 또한 유도전동기의 구름베어링시스템의 비정상적인 상태에서 고정자전류을 검출하기 위하여 TMS320F2407 DSP 칩을 이용하여 데이터 획득보드를 개발하였다. 이 고정자전류신호를 해석을 통하여 베어링 손상을 검출하기 위한 방법으로 FFT, 웨이브렛 분석 및 내적에 의한 평균 신호패던에 의한 분석결과를 제시하였다. 특히 내적에 의한 신호분석을 통하여 베어링 손상 여부를 실시간으로 진단할 수 있는 새로운 알고리즘과 분석방법을 제시하였다.

DSP 마이크로컨트롤러를 사용한 CAN 네트워크 기반 유도전동기고장진단 시스템 설계

Induction motors are a critical component of many industrial processes and are frequently integrated in commercially available equipment. Safety, reliability, efficiency, and performance are some of the major concerns of induction motor applications. Fault tolerant control (FTC) strives to make the system stable and retain acceptable performance under the system faults. All present FTC method can be classified into two groups. The first group is based on fault detection and diagnostics (FDD). The second group is includes of FDD and includes methods such as integrity control, reliable stabilization and simultaneous stabilization. This paper presents the fundamental FDD-based FTC methods, which are capable of on-line detection and diagnose of the induction motors. Therefore, our group has developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. This paper presents its architecture. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module processes the stator current, voltage, temperatures, vibration signal of the motor.

A high-performance EIT system

This paper presents the development of a new electrical impedance tomography system for online measurement of two-phase flows with axial velocities up to 10 ms/sup -1/. The system is designed in a modular fashion and can consist of several data acquisition modules and computing modules. The data acquisition module includes a voltage controlled current source with a direct-current-restoration circuit, an equal-width pulse synthesizer unit and a synchronized digital demodulation unit. A new concept of current switching scheme is developed to enhance the ac coupling speed. The computing module includes a digital signal processor (TMS320C6202/6713) with memory, multichannel buffered serial ports and an IEEE1394 communication interface. Several DSP modules can be pipelined for a series of tasks ranging from measurement control to image reconstruction to flow velocity implementation. The performances have been tested and some trial results are reported. A data acquisition speed of 1164 dual-frames (2.383 million data points) per second has been achieved with a root mean square error less than 0.6% at 80 kHz in static test application. An application in the measurement of vertical oil-in-water pipe flow is reported.

V2-based power tracking for nonlinear PV sources

The photovoltaic generator exhibits a nonlinear i/v characteristic and its maximum-power point varies with solar insolation. A V2 based MPP tracking scheme is developed using a SEPIC topology. Mathematical models are formulated and a tracking algorithm then is evolved. A combined photovoltaic-system simulation model is developed in the SIMULINK. For a given solar insolation, the tracking algorithm changes the duty ratio of the convertor such that the solar-cell-array voltage equals the voltage corresponding to the maximum-power point. This is done by the tracking algorithm, which mainly computes the power, proportional to the square of the terminal voltage, and changes the duty ratio of the convertor so that this power is a maximum. The proposed algorithm is implemented in real time with the help of an analogue device DSP module. Results are obtained for different types of loads, including battery and other nonlinear loads. Experimental investigations are carried out for different numbers of samples and an optimum number of samples is found which results in the minimum magnitude of steady-state oscillations. It is shown, experimentally, that tracking of the maximum-power point can be achieved within 200 ms. The proposed peak-power-tracking effectiveness is compared with that of the conventional ‘VI’-based tracking scheme.

New approach to develop a system solution for an integrated multi-service system

This paper presents a system solution for an integrated multi-service system (IMSS) in the field of digital TV (DTV). Key element of this system is a motion picture media processor which is based on an integrated RISC CPU, scalable DSP modules and dedicated hardware units. This concept is targeted not only for the pure reception of digital TV, but also for the interactive processing of broadcasted data. High computational performance and scalability realize the enabling functionality for new media applications.

A parallel computer based on simple DSP modules

This article reports on an engineering project at the TUHH aimed at providing a massively parallel experimental computer system to support a number of research projects. The computer nicknamed the PENTAGON is an MIMD system containing a number of identical processing elements (PE's) linked via interfaces. The network is a 3-D torus, and the nodes are based on off-the-shelf signal processor chips, namely TMS 320C40's from TI. The design adds to these standard ingredients an engineering discipline to keep things as simple as possible, and a corresponding, quite unusual physical setup of the total system. These make up for a very cost effective system showing how simple it may be to build a powerful parallel machine. Although based on a standard architecture, the PENTAGON design takes some special choices, the most important being the complete distribution of I/O capabilities. This provides for an unlimited I/O bandwidth, the support of realtime applications and excellent capabilities of expansion. A graphics interface has been designed to provide direct realtime output from the DSP's. Another recent extension is a set of Power-PC modules on top of the DSP nodes. Besides standard commercial compilers for 'C40 networks, the functional language Fifth of the author has been implemented on the PENTAGON. Fifth provides facilities such as distributed objects and the automatical distribution of parallel programs. For well parallelizable applications such as the calculation of a Mandelbrot set, high efficiencies in the usage of the processors have been obtained.