DSP Applications Research Articles

FIR Filter Design using Floating Point Column Bypassing Technique

This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.

Delay Efficient Vedic Multiplier for DSP

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

Design of High Speed 32-bit Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

Application Analysis of Digital Signal Processor DSP in Logging Instrument

In today's world, the development of economy has led to the continuous development and evolution of science and technology. Computer technology and large-scale integration technology have been well developed and applied, followed by the technology of digital signal processing DSP production and application. In the field of logging, the application function of this technology plays a key role. It not only allows the imaging logging technology to be further developed, but also enables fast and accurate processing of downhole signals. Therefore, among many logging tools today, digital signal processing DSPs have been widely used, and their functions have been fully utilized. This paper analyzes the application of signal processor DSP in logging instruments. It is hoped that it can play a reference role in the good application and development of logging instruments.

Asic Implementation of 12-Bit Radix-8 Booth Multiplier

Multipliers are playing a vital role in DSP and Neural Networks applications. Many methods have been introduced to work on multipliers that offer high speed, less power consumption and reduced area. Booth Algorithm demonstrates an efficient way of signed binary multiplication. In this paper, physical design of 12-bit radix-8 booth multiplier for signed multiplication is presented with an aim to improve the performance metrics such as power, area and delay. The performance of 12-bit radix-8 booth multiplier is compared with the 64-bit radix-16 booth multiplier.

Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

Power and Area have always been topics of major concern in VLSI. Multipliers and adders form the most vital units for a variety of DSP applications. Hence reducing the power consumption of the multiplier blocks can aid us in reducing the total power consumed by these applications to a large extent. One of the best techniques to do so is by bypassing of the multiplier blocks. Besides bypassing, approximate computing can also help in increasing power and area efficiency for error tolerant applications. This paper aims at designing a multiplier which gives a better performance in terms of area utilization, power consumption and power-delay product as compared to the existing multipliers. Four bypassing techniques namely, Row bypassing, column bypassing, row and column bypassing and two-dimensional bypassing already exist in the literature. These techniques were extensively studied and simulated in Cadence Virtuoso tool, followed by modification of two-dimensional bypassing multiplier using the concepts of approximation and bypassing. Further, validation of results for multimedia and image processing applications is done by obtaining the PSNR values of an image contrasted using the proposed multiplier.

A Scaler Design for the RNS Three-Moduli Set {2n+1−1,2n,2n−1} Based on Mixed-Radix Conversion

Adopting the moduli set [Formula: see text] for different DSP applications instead of the traditional moduli set [Formula: see text] has the advantage of excluding modulus [Formula: see text]. A multiply-and-accumulate modulo [Formula: see text] unit is more demanding than a modulo [Formula: see text] unit, which signifies the importance of this adoption. This paper introduces a new design for a scaling unit “Scaler”, that deals with the arithmetic-friendly residue number system (RNS) moduli set [Formula: see text]. The scaling factor is the power-of-two moduli [Formula: see text]. The scaling algorithm is based on the mixed-radix conversion (MRC) technique, which converts RNS-based representation into a weighted representation. The proposed approach is compared with other functionally-identical or functionally-similar scalers that perform scaling for the same moduli set under consideration or for the moduli set [Formula: see text]. The comparison is carried using theoretical unit-gate approach and experimental VLSI layout approach. The proposed scaler is shown to be more area and power-efficient than recently published competitive works.

Mathematical Model of Multirate Signal Processing Concept on down/up Sampling Multistate and Polyphase Decompositions for DSP and Digital Communication Application

Mathematical Model of Multirate Signal Processing Concept on down/up Sampling Multistate and Polyphase Decompositions for DSP and Digital Communication Application

A High-Speed Wide Fan in Approximate Reverse Carry Propagate Adder for Energy Efficient DSP Applications

A High-Speed Wide Fan in Approximate Reverse Carry Propagate Adder for Energy Efficient DSP Applications

FPGA Implementation of Floating Point Based Cuckoo Search Algorithm

Cuckoo search algorithm (CSA) has been a candidate for numerous recent applications and showed great compatibility in solving optimization problems. It is a metaheuristic algorithm which is based on the odd breeding strategy of the Cuckoo bird spices. It is used to find an optimum or near optimum solution for a certain problem. In this research, we propose an FPGA hardware implementation for the CSA based on single precision IEEE floating point (FP). The FP format provides a wider range and higher precision when compared to fixed point format. To the best of our knowledge, this is the first study to consider implementing FP format-based CSA on FPGA. The proposed design is implemented using pipelined and parallel techniques to get a high throughput and speed. The design is controlled and coordinated using finite state machines (FSMs) modules and is configured on Cyclone IV E FPGA chip from Intel. Three common benchmark functions are used to evaluate the performance of the proposed design. The design has a maximum operating frequency of 99 MHz. It was found out the maximum power consumption for the most complex function is 610.28 mW, mainly due to the use of FP format. In addition, the proposed design is implementation and evaluated for multidimensional operation. Accordingly, the proposed design is suitable for path planning for unmanned aerial vehicles (UAVs), sensor deployments for wireless sensor networks (WSNs) in addition to medical diagnostic and DSP applications.

Distinctive Phonetic Features Modeling and Extraction Using Deep Neural Networks

Feature extraction is a critical stage of digital speech processing systems. Quality of features is of great importance to provide a solid foundation upon which the subsequent stages stand. Distinctive phonetic features (DPFs) are one of the most representative features of the speech signals. The significance of DPFs is in their ability to provide abstract description of the places and manners of articulation of the language phonemes. A phoneme's DPF element reflects unique articulatory information about that phoneme. Therefore, there is a need to discover and investigate each DPF element individually in order to achieve a deeper understanding and to come up with a descriptive model for each one. Such fine-grained modeling will satisfy the uniqueness of each DPF element. In this paper, the problem of DPF modeling and extraction of modern standard Arabic is tackled. Due to the remarkable success of deep neural networks (DNNs) that are initialized using deep belief networks (DBNs) in serving DSP applications and its capability of extracting highly representative features from the raw data, we exploit its modeling power to investigate and model the DPF elements. DNN models are compared with the classical multilayer perceptron (MLP) models. The representativeness of several acoustic cues for different DPF elements was also measured. This paper is based on formalizing DPF modeling problem as a binary classification problem. Because the DPF elements are highly imbalanced data, evaluating the quality of models is a very tricky process. This paper addresses the proper evaluation measures satisfying the imbalanced nature of the DPF elements. After modeling each element individually, the two top-level DPF extractors are designed: MLP- and DNN-based extractors. The results show the quality of DNN models and their superiority over MLPs with accuracies of 89.0% and 86.7%, respectively.

Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications

Coarse grained reconfigurable architecture got the attention of researchers working in designing computing architectures for processing massive streaming data associated with the multimedia applications in portable entertainment and communication electronics. The algorithms for processing audio, video, and graphics are very complex in nature. These data intensive computation algorithms belong to the domain of signal processing. As the complexity of algorithms increases, a matching improvement in speed performance of the hardware becomes essential to maintain the quality of service. The observed growth of algorithmic complexity is much higher than the growth rate of integration density governed by Moore’s law. Also, the constraints on memory bandwidth in the traditional von Neumann architectures along with the slow growth in the battery capacity demands a paradigm shift in computer architecture design. Reconfigurable hardware architecture is proposed as a possible alternative in this regard. The reconfigurable architectures are designed to exploit the regular and repetitive structure of signal processing algorithms and the coarse grained processing elements are designed to match with the word level granularity of these complex algorithms. The research shows that the coarse grain reconfigurable architectures with heterogeneous processing elements are a better option for system design in DSP applications which exploit granularity matching between the algorithms and the processing hardware, and also the inherent parallelism of DSP algorithms for the realization of low power DSP systems.

Multi Design Exploration and Register Minimization of Retimed Circuits Using GA in DSP Applications

Multi Design Exploration and Register Minimization of Retimed Circuits Using GA in DSP Applications

DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications

In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.

VLSI Architecture for DSP Application

VLSI Architecture for DSP Application

A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation

Fixed-width multipliers are intensively used in many DSP applications whose accuracy and energy efficiency affect the whole digital system to a large extent. To improve the computation accuracy, a Booth-encoded sign-digit-based conditional probability estimation approach is proposed. A symmetric error distribution is obtained by taking the sign bit of the Booth-encoded multiplier into consideration when applying the conditional probability. In addition, a more generalized mux-based estimation method is formulated for the circuit implementation, which reduces the delay time and power dissipation. Simulation results show that the proposed multiplier exhibits the best computation accuracy with the least energy per operation. It performs even better for those operand lengths that are not multiples of 4. The maximum reduction on energy-delay-error product can reach 14.8% compared with all its contenders among various operand lengths.

FPGA Implementation of High Speed Digital FIR Filter

Multipliers play an important role in today's digital world especially in DSP and DIP applications. With advances in technology, many researchers are trying to design multipliers which offer either of the following targets-high speed, low power consumption, regularity of layout and less area or even combination of them in one multiplier. Now-a-days researchers are focusing on low power and high speed. This may be possible by designing effective multiplies as these are involved in huge amount in almost all DSP architectures. To do so many multipliers are available such as Booth multiplier and Wallace tree multiplier. Booth multiplier gives high performance (accuracy) but with high delay, whereas Wallace tree multiplier gives high speed but with less accuracy.The proposed method of CSD multiplication has the ability to reduce truncation error, computation latency for constant word length multiplications. Furthermore Horner CSD multiplier with pipelining concept makes multiplier design power efficient and speed efficient. This novel CSD algorithm is used here to design a Digital FIR filter and the same is designed with the booth and Wallace tree algorithm and compared. It is observed that proposed design is better w.r.t no. of slices and delay in comparison with existing methods. This design is coded in Verilog HDL and targeted on the spartran-3 device of XILINX 14.5.

Design and implementation of least mean square algorithm for a new reconfigurable FIR filter architecture

Nowadays, the communications and computations has been performed by Digital Finite Impulse Response (FIR) filter. FIR filter is predominantly used in DSP applications for efficient implementations. FIR filter is able to declare a firm linear phase frequency characteristic with any type of amplitude frequency characteristic in a DSP system. A reconfigurable FIR filter architecture has been implemented using Least Mean Square (LMS) algorithm in the proposed scheme. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method has been implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE Design Suite 12.4.

Energy Efficient Quality Tunable CORDIC for DSP Applications on Battery Operated Portable Devices

COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

Field Programmable Gate Array Softcore Processors Optimised for Digital Signal Processing Applications

The benefits of adding explicit DSP operation support to an FPGA-based softcore processor are examined. An experimental DSP processor has been designed, implemented, simulated, and verified on a Xilinx Virtex-5 XC5VSX50T FPGA chip. An initial very simple architecture is upgraded with different supporting hardware to enhance the processor's performance in execution of DSP applications. These hardware enhancement techniques include a specialist execution unit, modification to the memory architecture, adding an extra address control unit, upgrading with more active addressing modes, and extending the instruction set with zero-overhead looping support. These enhancements reduce the number of instructions used in the inner loop of convolution-based DSP algorithms to a single instruction. By using these proposed enhancement techniques, the overall performance was improved by an average of 9 times (800% improvement) in FIR Filter and Matrix Multiplication benchmark DSP applications. The overall area increased by about 1.41 times (41% extra cost). Using in-built DSP blocks in the FPGA instead of logic blocks to implement the arithmetic unit of the processor reduced the power consumption by 14% from 840 mW to 725 mW.