Driver Circuit Research Articles

Design of Nanosecond Pulse Laser Diode Array Driver Circuit for LiDAR

The pulse laser emission circuit plays a crucial role as the emission unit of time-of-flight (TOF) LiDAR. This paper proposes a nanosecond-level pulse laser diode array drive circuit for LiDAR, primarily aimed at addressing the issue of high-speed scanning drive for the laser diode array at the emission end of solid-state LiDAR. Based on the single pulse laser diode drive circuit, this paper innovatively designs a circuit that includes modules such as a boost circuit, linear power supply, high-speed gate driver, GaN field-effect transistor, and pulse narrowing circuit, realizing an 8-channel laser diode array drive circuit. This circuit can achieve a pulse laser array drive with a single channel operating frequency of greater than 100 kHz, an output pulse width of less than 5 ns, a peak power greater than 75 W, and a channel switching time that does not exceed 1 μs. A field programmable gate array (FPGA) is used to control the operation of this circuit and perform a series of performance tests. Experimental results show that this circuit has a high repetition rate, large output power, a narrow pulse width, and fast switching speeds, making it highly suitable for use in the optical emission module of solid-state LiDAR.

Frequency linearization of voltage controlled oscillator (VCO) for 2 µs frequency modulated continuous wave (FMCW) reflectometer.

Frequency modulated continuous wave reflectometers have been widely used to measure plasma density profiles in many magnetic fusion devices. The frequency modulation (FM) time of the KSTAR reflectometer was 20 µs, that is, the FM rate was 50kHz. However, the edge density of the KSTAR tokamak fluctuates typically over the frequency range of 20-50kHz in the ELMy H-mode plasmas. Therefore, the density profile changes significantly during the FM time, causing significant distortion in the density profile measurements. The FM rate must be increased at least ten times faster than the density fluctuation frequency. A new voltage controlled oscillator (VCO) driver is designed based on the AD8067 operational amplifier to achieve a FM time of 2 µs. The VCO output frequency is linearly modulated by predistorting the tuning voltage of VCO using a 400 MSamples/s arbitrary waveform generator. The resulting output frequency of the VCO is measured by mixing the VCO output with a fixed frequency synthesizer signal and measuring the mixer intermediate frequency using a 2.5 GSamples/s digitizer. The tuning voltage is adjusted to minimize the amount by which the measured frequency deviates from the linearly modulated frequency. A simple linear adjustment proportional to the deviation does not effectively suppress the nonlinearity in FM. The response time of the VCO driver and the VCO input interface should be taken into account by solving the entire circuit equation. In this paper, the developed VCO driver circuit and the frequency linearization method are described.

Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting

Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting

High-yield Micro-LED laser transfer accomplished using an ablation-type release material

Micro light-emitting diode (Micro-LED) is a highly promising technology in the field of new displays, with the mass transfer process involved in its manufacturing process widely regarded as a major barrier to their further development. This study adopts laser transfer technology as the primary solution, using ablation-type transfer release materials that improve chip utilization rates over blister-type release materials. In addition, measurement of the laser transfer parameters, inspection, and laser repair technology are combined to achieve a transfer yield of about 100% to the carrier substrate and a cumulative transfer displacement of less than 1 µm in the Micro-LED inverted chip array. Furthermore, cleaning agents were used to remove adhesive residue from the receiving substrate after transfer, improving the bonding yield between the chip and the thin film transistor driver circuit board. This study provides a feasible solution for Micro-LED mass transfer, which could boost its further development toward commercial application.

Region‐selective shift register by a single output enable signal for a multiple refresh frequency driving scheme

AbstractMany low‐power technologies have been developed for high‐performance displays. One method is to vary the refresh rate according to the input image, where frequencies are reduced over still images and slow‐moving videos. To support the variable refresh rate scheme, the programmable gate driver circuit should be integrated. This paper proposes a thin‐film transistor (TFT) shift register of which output pulse is simply controlled by an enable signal. Because the output pulse generation is directly adjusted without the previous programming period, various output pulse sequences are possible with the high flexibility. The shift register is composed by adding six TFTs and one capacitor to a conventional circuit that provides a carry pulse to a next stage. The simulation program with integrated circuit emphasis (SPICE) simulation ensures that gate pulses for any numbers of lines in any regions can be generated within one frame only by applying the enable signal at the corresponding timing, resulting in multiple refresh frequencies in a screen. In addition, it is verified that additional TFTs and capacitor contribute to only the negligible increase in power consumption by 2.1%, compared to a conventional shift register.

Design of PNP SiGe HBTs Towards 200 GHz fmax

Engineering SiGe HBTs with very high fT and fmax poses a significant challenge in the industry. Most technology iterations focus primarily on the improvement of the NPN performance for RF amplifiers, and a fast PNP device is often never offered. It is even more difficult to make high performance SiGe PNP transistors with comparable performance due to fundamental material and electrical limitations. However, the availability of a complementary device can enable several circuit applications including matched driver circuits and push-pull amplifiers. This paper applies lateral and vertical optimizations in a SiGe PNP, explores the performance scaling available and demonstrates a measured peak fT /fmax performance of 130/180 GHz at a BVCBO of 5.1 V.

Distortion-tolerant on–off keying preemphasis signal transmission for a 10 Gbps indoor visible light communications

Abstract The design and simulation of indoor visible light communication (VLC) system with preemphasis is proposed for 5 m transmission of signal at the data rate of 10 Gbps for receiving only applications like smart TV, smart speaker, and smart home appliance control. The preemphasis driver circuit is designed to reduce the intersymbol interference by pulse shaping the signal and transimpedance amplifier is used to amplify the signal for longer distance transmission. Intensity modulation at the sender side and direct detection at the receiver-side are adopted in this work for the improvement of the system’s overall performance and to decrease its implementation cost. The system performance is analyzed in terms of BER, data-rate, Q-factor, and eye diagrams. The setup is developed, which includes a nonreturn-to-zero (NRZ) generator, preemphasis driver, light-emitting-diode, VLC channel, and receiver with an avalanche photodiode and Gaussian LPF. At 10 Gbps data rate, the maximum transmission distance that can be obtained is 5 m with a BER of less than 10−31.

An analog switch circuit structure suitable for low-distortion transmission

Abstract A MOSFET analog switch circuit structure suitable for low-distortion bidirectional signal transmission is proposed. By introducing a “threshold voltage matching MOSFET” into the MOSFET switch driver circuit structure, the driving voltage corrected by the threshold voltage is generated by the driving circuit, eliminating the problem of poor conduction on-resistance flatness in traditional analog switch circuit structure due to MOSFET second-order effects and non-constant overdrive voltage. The circuit completed schematic and layout design based on the 0.13 μm BCD process. Simulation results show that the switch has bidirectional transmission capability, with a typical on-resistance value of 115 Ω. It achieves less than 5% on-resistance non-flatness under resistive loads ranging from 500 Ω to 1 KΩ, which is more than 50% improvement compared to traditional analog switch structures. Moreover, the on-resistance flatness is insensitive to changes in load and temperature.

Research on Characteristics Matching of Micro-LED Devices

This paper presents the design of a 40 × 40 micro-light-emitting (micro-LED) test array based on a 20 mm × 20 mm substrate. A study of the relationship between luminous brightness, driving current, and driving voltage revealed that the data voltages of the red, green, and blue micro-LED array from 0 to 255 grey levels are 0.31 V, 0.29 V, and 0.30 V, respectively, under the condition that the target brightness of the white field is 1000 nits and the color temperature is 9300 K. The brightness range of the red micro-LED array is 64.8–101.2%, the brightness range of the green micro-LED array is 66.5–102.8%, and the brightness range of the blue micro-LED array is 53.5–129.2%. In order to overcome the luminance nonuniformity, a grey level depth of 12 -bit is required. A 10T3C pixel driver circuit based on low-temperature polysilicon (LTPS) with a depth of 12 bits greyscale is designed and fabricated into the micro-LED display. A brightness uniformity of 84.1–97.1% can be achieved by brightness correction combined with a 12-bit greyscale depth system for micro-LED display. This provides a valuable reference point for subsequent improvements in the quality of micro-LED displays.

Efficient power conversion with four switch soft-switching boost integrated half-bridge dual-output series resonant converter

Soft switching reduces voltage and current stress during transitions, smoothing and quieting operations and reducing electromagnetic interference while also increasing efficiency and equipment lifespan. Circuit design, component selection, and switching frequency optimization affect power electronics soft switching. This paper proposes boost integrated half-bridge dual-output series resonant (BIHBDOSR) converter, a novel converter design and control method to increase series resonant converter performance by reducing storage element size, switch count, and switching losses. This methodology relies on soft-switching technologies like zero-voltage switching (ZVS) and zero-current switching (ZCS). These methods use class-D, class-E, series, parallel, and series–parallel resonant converter circuits to increase efficiency and minimize component stress. The proposed converter is ideal for constant voltage, constant power, and current-controlled loads with the output voltage being regulated by a closed-loop PI controller. The output voltages for two loads in the simulation depart from reference values. V01 changes from 14 to 20 V and V02 from 18 to 15 V at 300 ms owing to switching variances. The proposed converter utilizes gate driver circuits, resonant tank circuit, current sensor, FPGA board for closed-loop control, and current sensor for stability, ensuring converter stability. The proposed converter closed-loop control method modifies PWM signals to regulate both loads independently and ensure steady output voltage. Additionally, to validate the effectiveness of proposed converter, a 50-W driver circuit is designed, delivering two independent outputs of 20 W and 30 W. Frequency modulation (FM) and duty cycle control methods are employed to obtain the desired outputs.

Experimental implementation of Speed Stabilizer Based Field Oriented Control of Brushless DC Motor for Scooter Applications

An electric scooter, as one type of Lightweight vehicles technology, is a motorized vehicle designed for short-distance travel and recreational purposes. It is powered by an electric motor and typically has a rechargeable battery that provides sufficient power to operate the vehicle. Electric scooters are similar to traditional scooters but are much quieter, eco-friendly, and more energy-efficient. They are commonly used as an alternative mode of transportation for commuting, sightseeing, and recreational activities. This work presents an experimental implementation of speed stabilizer of electric scooter. In fact, a constant speed function might be required in a specific case in the operation of the scooter. A Field Oriented Control (FOC) method was chosen to control the speed of 3-phase Brushless DC motor of the scooter using a PIC16F873A Microcontroller through a Driver circuit. The control algorithm is designed to produce pulse width modulation (PWM) signal with the PID controller of the pulse bandwidth equipped with this Microcontroller and compared to the return pulse of the speed sensor in order to create and apply a closed back-feed system for good stability performance of scooter speed at different load values. The results obtained from this work show that the possibility of obtaining a wide range of control of the speed of the scooter at different loads with high reliability.

Performance Comparison and Analysis of Four- and Six-Switch Inverter Controls of BLDC Motor Employing Deep Learning

Robust and effective control of brushless dc (BLDC) motors is paramount in modern-day motion control. The BLDC motor is known for its high speed, high torque, small size, low noise, and equally low maintenance requirements compared to the brushed DC motor. Nowadays, it can be found in the areas of robotics, aerospace, military, and industrial machines, among others. In this paper, two inverter topologies, the threephase six-switch driver circuit (TPSSDC) and the three-phase four-switch driver circuit (TPFSDC), are used to drive and control the speed of the BLDC motor. For the control technique, however, a fitting neural network from the deep learning (DL) toolbox is employed to train and improve the speed performance of the motor. Both TPSSDC and TPFSDC are simulated and tested in MATLAB Simulink, and the resultant output is analyzed graphically and analytically. Graphical observation shows that the TPSSDC control approach is superior in terms of reference tracking and has less ripple, and better rise and settling times when compared to the TPFSDC control approach, however, the TPFDC is considered for its low cost and simple circuitry. Numerically, the TPSSDC also outperforms at 1000 rpm with a 1.685 ms rise time and a 1.420 ms settling time compared to the TPFSDC, which rises at 6.526 ms and settles at 5.237 ms. At 3000 rpm motor speed, the TPSSDC is better, having a rise time of 5.815 ms and settling time of 4.048 ms, when compared to the TPFSDC, which rises at 11.277 ms and settles at 10.067 ms.

High accuracy line following intelligent car based on infrared sensor

This research aims to describe the design and construction of a line-following intelligent automobile using the TM4C123GH6PZ microcontroller as the central processing unit. The vehicle uses two MG310P20_7 motors, one motor driver circuit and a 12-gray sensor for propulsion, motor control and line detection. The sensors made the high-accuracy angler movement in tests, the vehicle is 91.85% stabile to follow the line, taking an average of 3.44 seconds to complete a 3-meter road. Therefore, this concept demonstrates how infrared sensors and sophisticated control algorithms can be used to be more stable in creating driverless vehicles.

DC-biased Suzuki stack circuit for Josephson-CMOS memory applications

Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables.

Performance Investigation of 17 Level Reduced Switch Count Multilevel Inverter

The primary objective of this paper is to introduce a 17-level multilevel inverter with only eight power switches and three diodes that can be suitable for electric vehicle applications. This setup utilizes three distinct unequal DC sources to create the 17 levels of output voltage waveforms. The modes of operations of the proposed topology have been discussed in detail. The calculation of conduction losses, switching losses, efficiency, total standing voltage, and cost function per level for the suggested inverter has been elaborated. Due to more semiconductor power switches, diodes, capacitors, driver circuits, and DC sources in typical inverters, switching losses, costs, and harmonic distortion are increased. The nearest-level control technique has been utilized to control the switching elements of the recommended configuration. The performance comparison of various multilevel inverter topologies has also been discussed. The suggested multilevel inverter provides a higher efficiency of 98.60%, cost function of 3.6 for a weight coefficient of 1, improved power quality, and higher reliability. A reduction in the power switches significantly reduces the convolution of switching circuitry. The total harmonic distortion produced by this inverter is 3.49%, which comes under the IEEE standard of 5%.

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28 nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).

A New Multiresonant Gate Driver Circuit for SiC MOSFETs

A New Multiresonant Gate Driver Circuit for SiC MOSFETs

Comparative Study of TLP250 and IR2132 Driver-Based Inverter for Induction Motor Driving

As time progresses, electric motors are used for industrial or commercial purposes. The need for a motor that is robust, simple, and easy to maintain has been answered by creating an induction motor that can handle the purpose. At the beginning of its use, induction motors were more often used at constant speeds. Using an inverter becomes one of the solutions at hand to control the induction motor. Nowadays, most inverters are controlled by the SPWM (Sinusoidal Pulse Width Modulation) method. This method can adjust the output voltage and frequency by setting the carrier signal's frequency value and the reference signal's amplitude. A driver circuit is needed to implement an SPWM-based inverter. This driver circuit is needed to isolate the power circuit from the controller. Moreover, this circuit is also used to increase the microcontroller output signal to trigger the IGBT gate switch. The IR2132 and TLP250 drivers are often used in three-phase inverter applications. These drivers have advantages and disadvantages. This paper discusses the capabilities of these two drivers when applied to a three-phase inverter that functions as an induction motor drive. This inverter-controlled induction motor is advantageous because it can be rotated at a nominal speed and frequency.

Review of Integrated Gate Driver Circuits in Active Matrix Thin-Film Transistor Display Panels.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

Dual-bootstrapping gate driver circuit design using IGZO TFTs

To promote the integration of thin-film transistor (TFT) gate driver circuit technology into high-resolution large-size display application with narrow bezel, achieving high speed is a critical challenge. This paper proposed a dual-bootstrapping TFT integrated gate driver circuit for large-size display. The over-drive voltage of the driving TFT was increased both at the rising and falling edges of the output waveforms. To validate the circuit feasibility, the proposed circuit was fabricated using amorphous indium-gallium-zinc-oxide (a-IGZO) TFT technology and measured in terms of transient response with cascaded stages and reliability tests over long operating time. Compared to conventional approaches, the proposed gate driver demonstrates a 39 % reduction in the falling time as well as compact layout. Therefore, the proposed gate driver schematic is well-suited for large-size display applications that involves heavy resistance–capacitance (RC) loadings and require high resolution above 8 K.