Driver Circuit Research Articles

PARAMETERS OF THE COMPONENTS OF THE HIGH VOLTAGE NETWORK OF ELECTRIC CARS
 AND THEIR CALCULATION

The article considers the components of high-voltage networks of electric cars and their relationship with
 the components of low-voltage networks, as well as the methods of their conversion. The dependence of the weight and
 size parameters on the voltage of the electric car high-voltage network is shown. The calculations showed the
 possibility of using the "voltage drop" parameter in the wires to control the current strength without using additional
 shunts. The distinctive features of the output power switches and the inverter driver circuit are shown. The operation
 of a single-phase bridge circuit with four different switching states is analyzed. The principle of organizing a sinusoidal
 form using pulse-width modulation is shown, with a given oscillogram of the generated signal. The synthesis of a threephase
 alternating current system is shown. The parameters of the absolute and relative slip of the motor rotor are
 determined by reading the rotational speed and position of the motor rotor and the rotating magnetic field of the stator
 when reading from the output stages of the inverter.

Design of GPIO Transmitter

Abstract: This paper presents a comprehensive design approach for a versatile 1.8V GPIO transmitter tailored for a 5pf load capacitance. The work introduces a novel design that accommodates 1.8V IO supply, enhancing the flexibility and compatibility of the GPIO transmitter. The GPIO consists of a level shifter and a driver. A level up shifter is used along with a driver capable of driving the signals without any data loss. The work embarks on the objective of designing a robust GPIO transmitter by utilizing a combination of level shifting and driver circuitry. The methodology encompasses meticulous simulation-driven design, encompassing a 45nm technology node and the Cadence Virtuoso platform. The design incorporates a level shifter that elevates input data from a core domain operating at 0.8V to IO levels of 1.8V , ensuring seamless communication across various voltage domains. The driver circuit, implemented with progressive sizing, effectively drives the substantial load capacitance of 5pF, maintaining the integrity of input data. Through detailed analysis, the architecture ensures compliance with the demanding specifications of Intel Max 10 FPGA. Simulation results exhibit the efficacy of the proposed design. The level shifter successfully transforms an incoming 0.8V data signal to 1.79V , aligning with the 1.8V IO requirements. The driver also drives the same signal out with a load of 5pf. The level shifter and driver is combined to check for the working of transmitter, with input at 0.8V and the signal is obtained at the expected voltage level at the output of driver

A high boost switched capacitor multilevel inverter with reduced components

ABSTRACT Switched capacitor multilevel inverters (SCMLIs) became a popular DC-to-AC converter due to their unique features like self-capacitor voltage balancing and self-output voltage boosting abilities over conventional multilevel inverters in recent years. However, recently developed SCMLIs suffer from higher component counts, lower voltage boosting factors, higher total standing voltage, and the requirement of isolated DC sources for generating high-quality output voltage level waveform. These drawbacks make the inverter costly, complex, and bulky. To address these drawbacks of SCMLIs, a novel SCMLI is proposed in this paper. The proposed SCMLI can realise 17 output voltage levels with a higher boosting factor. In addition, the proposed SCMLI uses lower switches, driver circuits, capacitors, and diodes than similar SCMLIs. The proposed SCMLI also offers a cheaper cost function per output voltage level per boosting factor compared to others. A thorough description of the proposed inverter’s operating principle, voltage stress analysis, and capacitor selection procedure have been discussed. The proposed inverter’s cascaded form has been constructed and analysed for various DC source configurations. An extensive simulation study of 17-level SCMLI in MATLAB/Simulink platform and an experimental investigation on a 17-level laboratory prototype validate the proposed SCMLI’s merits and effectiveness.

Golden Bump Based Flip-Chip Interconnection for Superconducting Multi-Chip Module

This paper introduces the preparation of golden bumps on the single flux quantum (SFQ) circuit chip by using the 20-μm-diameter golden wire and the flip-chip (FC) bonding of the SFQ chip and the substrate by the ultrasonic bonding method. Firstly, a coplanar waveguide (CPW) flip-chip interconnect structure was designed and fabricated, and the low-temperature transmission performance i.e., S-parameters were tested. The results showed that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S₁₁</i> ≤ -10 dB and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S₂₁</i> ≥ -3 dB among the range from 100MHz to 52 GHz at 4.2 K. And the golden bump can transmit PRBSs of 5 Gbps, and its bit error rate (BER) is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . Secondly, the flip-chip bonded SFQ driver& receiver circuits with 4.7-Ohm impedance were prepared and the BER of the SFQ pulse signals were measured by the driver& receiver circuits. The test results showed a zero-bit error rate when the number of transmitted codes is in the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . The experimental results show that the golden bump based flip-chip interconnection has good high-frequency transmission performance, and can be used for high-bandwidth and narrow pulse signal transmission in superconducting multi-chip modules (MCMs).

Analysis and Suppression of Common Mode Interference in Flyback Switching Power Supplies

In the flyback power supply, with the increase of switching frequency, the electromagnetic interference caused by the power switch becomes more and more serious. In order to control the interference problem, the common mode (CM) interference noise source and transmission path of the flyback power supply are analyzed, the equivalent model of the transmission path is established, and the parameters affecting the common mode noise magnitude are deduced. On this basis, an active gate driver (AGD) circuit is proposed to suppress the noise generated by interference sources. The AGD circuit reduces the du/dt of the power switching tube by reducing the driving current during the turn-off dynamic period and thus achieves the reduction of the common-mode noise. Compared with traditional drive mode, the AGD can increase switching losses less at the same target. Finally, the feasibility of the AGD method is verified by experiments on the test platform.

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

&lt;span lang="EN-US"&gt;This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (&lt;/span&gt;&lt;span lang="EN-US"&gt;CMOS).&lt;/span&gt;

Design and Performance Evaluation of an Automatic Dimmable Fault-Adaptive LED Driver Circuit

In this paper, an automatic, fault-adaptive, and dimmable LED driver circuit and LED lamp module is designed and simulated. The designed LED driver can automatically operate and dim (18–72) W LED modules assembled with unknown series-parallel combination of 3 W LED chips on universal AC input (Vrms=(90–265) V, 50/60 Hz). The unique feature of the modelled LED driver circuit is its ability to monitor and detect failure of any connected LED chip and then adapt to provide optimised light output from the LED modules under faulty conditions. The proposed LED driver circuit and LED lamp module are simulated in MATLAB Simulink environment to evaluate the electrical performance. The operation of the simulated LED driver circuit from 100 % to 30 % of rated light output and during occurrence of fault is satisfactory and in compliance with IEC61000–3–2:2014 and IEEE Standard P1789. Input power factor of the simulated LED driver ranges from 0.74 to 0.99, THD from 3.33 % to 30.63 %, and output current ripple from 4.6 % to 20 % under operation of all connected LED modules.

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks

Evaluation of SiPM-based readout system with gain stabilization for TL dosimetry

As the silicon photomultiplier (SiPM) technology has developed and matured, it has opened up avenues for its use in various luminescence dosimetry applications. However, the temperature sensitivity of SiPMs needs to be considered in settings where a SiPM-driven system may be affected by heat, such as during thermoluminescence (TL) measurements. This study investigated the TL signal reproducibility and temperature dependence of SiPMs (3×3mm2,50μm) using a Risoe TL/OSL-DA-20 reader, a gain stabilizing driver circuit, and a data acquisition (DAQ) module. The signal variation was insignificant when the temperature varied by less than 2 °C. However, when there was no temperature control, the signal loss occurred due to increased dark counts. We assessed four commercial dosimeters and compared them to conventional TL detection via a photomultiplier tube (PMT) in terms of dose-response, detection limits, and TL glow-curve characteristics. The slope in the dose-response (i.e., sensitivity) of the SiPM-based system was 1.5 to 3 times lower compared to PMT depending on the dosimeter. We explored the viability of TL readings by examining the potential reduction in sensitivity and dark counts due to the SiPM's photon-resolving feature. While the evaluation results of the suggested system demonstrate its practical usefulness, there are still unexplored areas that warrant further investigation. These are discussed in relation to the dark count rate, which is a major parameter that can impede the overall performance.

Performance Analysis of Harmonic-Reduced Modified PUC Multi-Level Inverter Based on an MPC Algorithm

Renewable and distributed energy generation includes wind turbines, fuel cells, solar cells, and batteries. These distributed energy sources need special power converters in order to connect them to the grid and make the generated power available for public use. Solar energy is the most readily available energy source; hence, if utilized properly, it can power up both domestic and industrial loads. Solar cells produce DC power, and this should be converted to an AC source with the help of inverters. A multi-level inverter for an application is selected based on a trade-off between cost, complexity, losses, and total harmonic distortion (THD). A packed U-cell (PUC) topology is composed of power switches and voltage sources connected in a series-parallel fashion. This basic unit can be extended to a greater number of output voltage levels. The significance of this design is the reduced use of power switches, gate drivers, protection circuits, and capacitors. The converter presented in this paper is a 31-level topology switched by a variable switching frequency-based model predictive controller that helps in achieving optimal output with reduced harmonics to a great extent. The gate driver circuit is also optimized in terms of power consumption and size complexity. A comparison of the 9-level and the 31-level PUC inverters is carried out to study the impact of the number of levels on the total harmonic distortion. The simulation results depict that the total harmonic distortion (THD) for a nominal modulation index of 0.8 is 11.54% and 3.27% for the 9-level multi-level inverter (MLI) and the 31-level modified packed U-cell multi-level inverter (MPUC-MLI), respectively. The reduction in THD is attributed to the increased number of steps in the output when using the model predictive controller.

Variable Amplitude Gate Voltage Synchronous Drive Technique for Improving Dynamic Current Balancing in Paralleled IGBTs

The problem of current sharing imbalance in the parallel connection of IGBT multi-modules affects the wide-scale application of parallel IGBT. The current imbalance problem in the dynamic process is mainly caused by the difference in control loop parameters. In parallel IGBT applications, current sharing is a critical concern. Objective differences in IGBT module and driver circuit parameters, as well as incomplete symmetry in the power circuit, lead to inconsistent parasitic parameters, resulting in both static and dynamic current-sharing issues. Static current sharing refers to the uneven distribution of load current under static operating conditions, while dynamic current sharing refers to the imbalance in current distribution among parallel IGBT modules during turn-on and turn-off processes. This is mainly influenced by the synchronization of turn-on and turn-off timings and the consistency of collector current change rates during these processes. The difference in characteristic parameters of IGBT modules is an important factor leading to the difference in control loop parameters, which has a profound impact on the dynamic current-sharing characteristics of IGBT parallel applications. In the case where the device parameters cannot be changed, some drive compensation controls can compensate for the influence of device differences on dynamic current sharing. Accurate identification of the characteristic parameters of the IGBT module is the key to this method. This paper mainly studies a synchronous variable-amplitude drive scheme and studies the influence of parameters such as synthetic gate resistance, gate-emitter capacitance, and on-off gate threshold voltage on the dynamic current-sharing characteristics. The correlation characteristics of the characteristic parameters of the IGBT device body are studied, and the characteristic model of each parameter and the influencing variable is constructed. The parallel working model of PSpice devices is established, and the influence of different characteristic parameters on the current-sharing characteristics is evaluated, and its sensitivity is summarized through simulation analysis. Through the 1700 V/300 A IGBT parallel switch characteristic experiment, the current sharing effectiveness of the synchronous variable amplitude driving method is verified. Finally, the effects of different gate control voltages and different action times on the dynamic current-sharing characteristics are summarized.

A fully integrated half-bridge driver circuit in All-GaN GAN-IC technology

To unlock the full potential of fast switching GaN technology, monolithic integration of power circuit is crucial. GaN-IC ensures a fast efficient switching operation by reducing the parasitic inductance of interconnections significantly. In this paper, we demonstrate a monolithically integrated half-bridge power switch with its corresponding driving stage and the protection circuits that is realized by using our GAN-on-SOI technology. A low gate threshold voltage along with a low gate overdrive makes the driving of a GaN HEMT difficult. An optimized gate driver design is important to fully utilize a GaN power switch. This is also crucial for overall system efficiency, robustness, and EMI performance. Along with the design description this paper discusses the challenges and the design considerations of the GaN power IC.

The development of a generalized multilevel inverter for symmetrical and asymmetrical dc sources with a minimized ON state switch

This paper proposes a double source double diode double switch (DSDDDS) multilevel inverter to generate positive voltage and a connecting polarity changing circuit of an H-bridge inverter to generate negative voltage. By connecting the jth number of basic units in series, the desired level is obtained. Various algorithms, such as Natural, Binary, Trinary, and Quasi-Linear sequences, and two proposed algorithms are discussed to determine the magnitude of DC voltage sources in order to generate more stepped levels with fewer switches. The proposed multilevel inverter eliminates the need to turn on additional power switches for different levels, which is the main advantages of this topology. The proposed multilevel inverter is compared to conventional switched diode multilevel inverters in terms of switch count, number of ON state switches per level, driver circuits, and total standing voltage. Real-time results from the OPAL-RT test bench and simulation have validated the proposed inverter.

Design and Performance Analysis of New Multilevel Inverter for PV System

Multilevel inverters (MLIs) have recently attracted more attention in medium-voltage and high-power applications as they can provide an effective interface with photovoltaic (PV) systems. Conventional MLIs are used to generate higher voltage levels, which improve power quality and reduce the requirement for passive filters. However, recent research has focused on designing new MLI topologies using reduced switch counts and less voltage stress. This study, as such, proposes a new nine-level symmetric MLI for PV systems with a minimum number of switches. This decrease in the number of switches reduces the voltage stress across the switches and the number of driving circuits, which lowers the complexity of the control circuit and, as a result, lowers the cost and size of the system. This article compares the proposed MLI with other topologies based on the DC sources, switches count, gate driver circuits (Ngd), total standing voltage per unit (TSVPU), cost function (CF), and components count per level (CC/L). The proposed topology is integrated with the PV system. MATLAB software is used to evaluate the performance of MLI at step change in irradiance and under variable load conditions. The total harmonic distortion (THD) of the proposed topology is reduced with the implementation of phase disposition pulse width modulation (PD-PWM). In addition, PD-PWM is compared with phase opposition disposition pulse width modulation (POD-PWM) and alternative phase opposition disposition pulse width (APOD-PWM) modulation techniques. The simulation results reveal the improved performance of the proposed topology at variable irradiance and under varying load conditions. The comparison results reveal minimum (TSVPU), CC/L, CF, and switch count compared to existing topologies. Hence, the proposed topology of MLI is cost-effective and superior in all aspects compared to other topologies. In summary, it offers overall improved performance, and thus, it is feasible for the PV system.

Topological Analysis and Solar Grid-Tied Integration of Level Building Network Based Extendable High Power Multilevel Converter

This paper presents a new solar multilevel converter (SMLC) with closed-loop control to integrate solar PV arrays with medium voltage 3.3 kV grid. This multilevel converter produces higher number of levels in the output voltage with less usage of semiconductor switches. This solar converter utilizes only ten switches and three PV sources with equal voltage to have seven levels in the output voltage. The main motive is to have minimum switches, which reduces the count of driver circuits for a power converter. Moreover, a reduced switch converter requires less space in terms of installing the power and auxiliary components. This solar power converter comprises a solar photovoltaic (SPV) array fed level building network (LBN) nested within the six switches connected in a rectangular arrangement. The converter has two PV sources at its upper and lower ends. This solar converter is also ideal for asymmetric configurations. Moreover, the increase in solar input power is possible with more count of the LBNs. The converter switching states and operating path demonstrate the working operation of the new solar PV system. A comparison of the proposed solar converter is made with existing multilevel topologies. The system is modeled and executed in closed-loop control to showcase its effectiveness for solar power conversion. The solar converter transfers the power in varying solar conditions successfully.

Indium–Gallium–Zinc Oxide Thin-Film Transistor-Based Scan Driver Circuit Using Separate Driving Structure for Multiple Output Signals

This article proposes a scan driver circuit based on indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) for multiple output signals. The proposed circuit could generate two overlapped output signals using a separate driving structure. The separate driving structure enabled the control nodes of each output signal to have a sufficiently high voltage during the output period. Consequently, the proposed circuit stably operated with the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{TH}}\text{)}$</tex-math> </inline-formula> varying from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3 to 4 V in the circuit simulation. The proposed scan driver circuit could reduce the circuit area because a single stage could output two output signals for two adjacent scan lines. Furthermore, the fabricated scan driver circuit exhibited a stable operation with multiple overlapped signals. Consequently, the proposed IGZO TFT-based scan driver circuit showed a stable circuit operation with multiple output signals through the separate driving structure.

A low characteristic impedance quasi-rectangular pulser based on solid-state inductive adder for High rEpetition rate Muon Source at CSNS

A solid-state inductive adder-based quasi-rectangular pulser featuring a low characteristic impedance has been developed in the laboratory to demonstrate the technical viability of using such a pulser for the HEMS muon source. The pulser consists of five layers connected in series, with each layer comprising 24 parallel branches. The paper mainly presents the design of the low characteristic impedance quasi-rectangular pulser from three aspects: primary driver circuit, coaxial central structure and transformer magnetic core. The experimental results show that through the careful design of the above three items, a quasi-rectangular pulse with fast rise and fall time can be achieved. The typical parameters of pulse voltage, pulse current, pulse flattop, repetitive rate, rise time and fall time at a charging voltage of 700 V are 3.5 kV, 560 A, 315 ns, 1 kHz, 47 ns, and 66 ns, respectively, on a 6.25 Ω matching resistor. In addition, the output characteristics of the pulser are investigated by varying critical parameters such as the charging voltages, the load resistances, and the number of parallel branches. The findings and results outlined in this paper offer valuable insights for the initial phase of developing an inductive adder pulser. They can aid in assessing the feasibility of the project, selecting critical parameters for essential components, and enhancing the output pulse's performance. A full-scale pulser with a peak pulse current of 3 kA and rise and fall time of ≤ 75 ns for HEMS muon source will be developed in the near future.

Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications

Spin transfer torque (STT) based magnetic tunnel junction (MTJ) device is a commercially appealing option for non-volatile latches and flip-flops. In this paper, an STT-MTJ based non-volatile latch with auto-writeterminate (AWT) feature is proposed. The proposed latch has a simple structure, better stability, and higher speed, and is easy to integrate with CMOS logic styles. Also, no additional write driver circuit is needed, resulting in a smaller footprint while writing into the MTJs. Therefore, the proposed latch consumes less power than earlier latches while using fewer transistors for a write operation and logic implementation. The proposed AWT circuit continuously monitors the write operation and prevents redundant MTJ writing and removes excessive write current flow, thereby saving write energy. The AWT circuitry can save the total write energy by ~83% when compared to the conventional write circuit. Also, the proposed circuitry for self-write termination uses 75% fewer transistors compared to previously proposed circuits.

Electromagnetic emission measurement prediction of buck-boost converter circuits using machine learning methods

ABSTRACT In this paper, a prediction system has been developed using machine learning techniques to obtain the conduction emission levels ensure they remain below the limit values specified in test standards. An LED (Light-emitting diode) driver circuit based on a buck-boost type DC-DC converter has been employed in the experiments. Standards-compliant conducted emission testing processes have been performed and measurement results have been used to generate datasets. These datasets have been organized and processed according to the targeted machine learning methods. GPR, has achieved the highest success rate of 99% among ANN and regression methods. In order to improve the performance in EMI harmonic prediction, training was conducted using deep learning, and the obtained model has a mean squared error of 0.78. The harmonics are well captured with the method and the results are in good agreement with measurements. Consequently, the number of required pre-compatibility tests for a similar topology can be significantly reduced.

A new symmetric modular eleven‐level inverter using single and double source unit for low voltage applications with reduced number of switches

AbstractThis study proposes a modular multilevel inverter for low‐voltage applications, including ac‐coupled renewables and energy storage systems. These inverters require many switches and gate drivers in their structures, which complicates the control system, reduces efficiency, and increases costs. This study introduces a new modular multilevel inverter that can produce five levels of positive voltage using only six power switches and five DC voltage sources. The basic unit is composed of a single‐ and double‐source (SDS) unit. SDS reduces the number of power electronic components, such as the insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocking voltage by switches. The proposed topology can boost the number of output voltage levels and decrease the number of switching devices and voltage stress using some combinations of basic submodules. The performance of the proposed 11‐level single‐phase inverter is compared with that of the conventional structures and recent symmetric topologies considering the number of switches, cost, and efficiency. The waveform quality and both the voltage and current harmonic characteristics were determined in accordance with IEEE 519–2014. Finally, an 11‐level prototype was constructed to validate the theoretical analysis, feasibility, and effectiveness of the proposed inverter.