Drift Chamber Electronics Research Articles

Modular pipeline readout electronics for the SuperBelle drift chamber

In order to explore new physics in B-meson decays we plan to upgrade the KEK B-factory to a luminosity of 5/spl times/10/sup 35/ cm/sup -2/ s/sup -1/. In parallel we are developing a new pipelined data acquisition system for the Belle detector to cope with higher trigger rates of up to 30 kHz and severe background conditions. In order to reduce development and maintenance costs, we have adopted a modular design for these new readout electronics. The chosen architecture consists of a common readout platform, upon which are mounted subdetector specific parts, customized to meet the readout requirements of each sub detector component. As an example of this new architecture, we present in this paper the design of drift chamber electronics. The drift chamber readout utilizes the AMT-3 time-to-digital converter chip, originally developed for the ATLAS experiment, which satisfies the performance requirement for current and future Belle drift chamber readout. A data transfer performance test with emulation modules, mounted on the common platform, shows that the new readout electronics works well at a more than 30 kHz input trigger rate.

The drift chamber electronics for the NA48 experiment

Drift chamber readout electronics for over 8000 channels with concurrent data recording and readout have been developed to update the NA48 experiment existing system. Drift times are measured in bins of 1.56 ns with respect to the continuously running 40 MHz experiment clock. The architecture is based on commercially available hardware for cost effectiveness and flexibility. The design of the electronics is described, and results from data-taking runs are presented.

The drift chamber electronics and readout for the NA48 experiment at the CERN SPS

A drift chamber readout system for a bout 8000 channels with continuous sensitivity, i.e. concurrent data recording and readout, is described. Drift times are measured in bins of 1.56 ns with respect to a continuously running 40 MHz clock. The clock interval of 25 ns is divided into 16 bins by means of a 16-element delay chain. The length of this chain is linked to the clock interval by a phase-locked loop. An ASIC chip was developed to perform time measurements and data storage for 16 channels. In an asynchronous readout of this chip, data are tranferred to intermediate buffers, for use in a first-level trigger and eventual final readout. The design of the electronics is described and results from data-taking runs are presented.

New drift chamber electronics for high energy gamma ray telescopes

The next generation gamma ray telescope is envisioned as a “2 meter class” instrument, a picture type detector using large area (2 m × 2 m) drift chambers for the imaging detector. Low power amplifier, discriminator and time-to-digital converter (TDC) circuits are crucial to the development of large area drift chambers for use in space where power is limited. We discuss the design for an amplifier, discriminator and quad TDC which will operate within an estimated power budget of 200 mW per anode for an instrument using large area drift chambers. The amplifier has a discriminator has a 12 ns propagation time, 15 ns rise time, 25 ns pulse width and 25 mW power. The quad TDC has a power of 95 mW, 12 bit resolution and RMS error less than 0.2% full scale.

Physical packaging and organization of the drift chamber electronics system for the Stanford Large Detector

The logical organization, physical packaging, and operation of the drift chamber electronics for the Stanford Large Detector are described. The system processes signals from approximately 7000 drift wires and is unusual in that most electronic functions are packaged on printed circuit boards within the detector. The circuits reside on signal-processing motherboards, controller boards, signal-transition boards, power-distribution boards, and fiber-optics-to-electrical conversion boards. The interaction and interconnection of these boards with respect to signal and control flow are presented. >

Front end and signal processing electronics for large detectors

The design of front-end electronic systems for experiments at very-high-interaction-rate colliding beams and fixed-target accelerators is discussed. Consideration is given to the preamplifier and shaping amplifier design, and to the optimal choice of technology, with particular emphasis on detectors with source capacitance in the range of 1-30 pF and for shaping times of 3-20 ns. Possible architectures of a two-level, on-chip buffering system which enable simultaneous, asynchronous data acquisition and readout with nearly no deadtime are discussed. Emphasis is placed on minimal power dissipation. A system of drift chamber electronics, with the goals of time resolution >

Drift chamber electronics with multi-hit capability for time and current division measurements

Drift chambers have been installed for luminosity measurements in intersection 5 of the SPS accelerator working in p p colliding mode. The required electronics is described. The system is able to process up to 16 hits per wire with a double pulse resolution of 40 ns; drift time and current division, with 1.25 ns and 1.6% resolution respectively, are recorded. Transconductance preamplifiers and discriminators are directly mounted on the chamber; 160 m of twisted-pair cable bring the signals to the digitizer unit. Coarse time is measured using RAM techniques, while fine time is obtained by means of a microstrip delay associated with a 100 K ECL priority encoder. Current division used a single 50 MHz Flash ADC which allows 26 dB dynamic range with 6 bit resolution. First operational results are reported.

Drift chamber electronics for time and pulse height measurements with multiple hit capacity

The electronic system developed for the read-out of jet chambers (JADE-collaboration, PETRA) is described. The system is able to process up to 8 hits per signal wire with a double pulse resolution of ∼ 100 ns. For each hit, the drift time and the integrated signals from both ends of the wire are recorded. The time measurement is performed using a MECL RAM technique, while the charge measurement is performed using gated integrators, fast analog memories and a 12-bit multiplexer-ADC system (one per 8 wires). Two-dimensional track coordinates and the energy loss of the particles passing the detector can be obtained.