DRAM Reliability Research Articles

Improving DRAM Reliability Using a High Order Error Correction Code

Improving DRAM Reliability Using a High Order Error Correction Code

DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips

To understand and improve DRAM performance, reliability, security, and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, stateof-the-art open source infrastructures capable of conducting such studies are obsolete, poorly supported, or difficult to use, or their inflexibility limits the types of studies they can conduct. We propose DRAM Bender, a new FPGA-based infrastructure that enables experimental studies on state-of-the-art DRAM chips. DRAM Bender offers three key features at the same time. First, DRAM Bender enables directly interfacing with a DRAM chip through its low-level interface. This allows users to issue DRAM commands in arbitrary order and with finer-grained time intervals compared to other open source infrastructures. Second, DRAM Bender exposes easy-to-use C++ and Python programming interfaces, allowing users to quickly and easily develop different types of DRAM experiments. Third, DRAM Bender is easily extensible. The modular design of DRAM Bender allows extending it to (i) support existing and emerging DRAM interfaces, and (ii) run on new commercial or custom FPGA boards with little effort. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability. In particular, we show that data patterns supported by DRAM Bender uncover a larger set of bit-flips on a victim row than those commonly used by prior work. We demonstrate the extensibility of DRAM Bender by implementing it on five different FPGAs with DDR4 and DDR3 support. DRAM Bender is freely and openly available at https://github.com/CMU-SAFARI/DRAM-B ender.

The Degradation of Characteristics in DRAM by ILD HDP Process Condition

As the size of DRAM devices are increasingly scaling down as time goes by, materials in the back end of line process are having a significant impact on DRAM device characteristics. [1]To ensure DRAM characteristics and reliability, it is necessary to identify the impact of subsequent processes. In this experiment, we studied the DRAM device electrical characteristics according to HDP CVD oxide process temperature which is used as ILD between metal lines in the back end of line.For the experiment, DRAM device wafer with a design rule of sub 20nm was prepared, and the p process temperature was divided into three way. (Ref, Ref -5%, Ref +5%)First of all, the concentration of the atomic bonding according to the process temperature was identified using FT-IR (Fourier Transform – Infra Red Spectroscopy).Through FT-IR, the presence of atomic bonding in the material can be identified and quantified.Next the electrical characteristics of the DRAM device according to the process temperature were evaluated with the corresponding sample.We measured capacitors leakage current and NBTI, which are important properties in DRAM devices.Fig 1 illustrates the tendency of hydrogen content to decrease as the temperature of HDP deposition increases.It seems that hydrogen out-gassing decreases as the HDP process temperature decreases, so that hydrogen in the film material diffuses in a subsequent thermal process.[2]Fig 2 shows a tendency for leakage current to increase as process temperature decreases. That means the leakage current increased as the hydrogen concentration increased.In addition, the EDS Test can prove the failure cell by capacitor leakage, and the result is that the same tendency was found in Fig 3.This is explained by the increase in trap density by hydrogen in Poole–Frenkel Emission among dielectric conduct mechanism. [3]The change in threshold voltage can be seen in Fig 4 according to the change in process temperature.Obviously, it is confirmed that hydrogen increase due to process temperature decrease has a significant effect on threshold voltage shift.As the hydrogen concentration increases, the Si-H bonds of interface are increased, then the Si-H bonds are broken after stress, contributing to NBTI degradation. [4]To summarize this experiment, changes in hydrogen concentration were observed with the temperature change of the HDP CVD process used as ILD.It has been confirmed that the increase in hydrogen concentration has greatly affected the increase in leakage current of capacitors and the deterioration of PMOSFET NBTI.ILD process temperature conditions have been identified as factors that have a clear effect on the characteristics of DRAM.We can propose the process conditions in the future, taking into account the characteristics.

A survey of techniques for improving error-resilience of DRAM

Abstract Aggressive process scaling and increasing demands of performance/cost efficiency have exacerbated the incidences and impact of errors in DRAM systems. Due to this, improvements in DRAM reliability has received significant attention in recent years from both academia and industry. In this paper, we present a survey of techniques for improving reliability of DRAM-based main memory. We classify the works based on key parameters to emphasize their similarities and differences. This paper is expected to be useful for computer architects, chip-designers and researchers in the area of memory/system-reliability.

Understanding Reduced-Voltage Operation in Modern DRAM Devices

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the data, and we comprehensively characterize the behavior of these errors. We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge). We perform detailed DRAM circuit simulations to validate and explain our experimental findings. We also characterize the various relationships between reduced supply voltage and error locations, stored data patterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism, called Voltron. The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance loss. Our evaluations show that Voltron reduces the average DRAM and system energy consumption by 10.5% and 7.3%, respectively, while limiting the average system performance loss to only 1.8%, for a variety of memory-intensive quad-core workloads. We also show that Voltron significantly outperforms prior dynamic voltage and frequency scaling mechanisms for DRAM.

Understanding Reduced-Voltage Operation in Modern DRAM Devices

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by manufacturers.

Analysis of heavy-ion induced charge collection mechanisms in SOI circuits

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate charge collection in SOI devices. Charge collection in capacitors and ICs can be induced by displacement currents caused by the release of charge in the substrate. The magnitude of charge collection depends on the geometry, gate surface area and oxide thickness of the device. It is mainly induced by the diffusion of carriers generated in the silicon bulk, which induces a voltage drop under the oxide surface. Carrier diffusion in low-doped silicon creates coupling effects between MOS elements separated by up to hundreds of microns. However, because of charge sharing effects, charge collection by displacement currents (by itself) does not appear to significantly affect SEU sensitivity in SOI devices. p–n junctions are far less sensitive to charge sharing effects than neighboring MOS structures. A mechanism that can significantly increase the SEU saturation cross section in SOI devices is charge release in non-ideally doped drain regions (not heavily doped throughout the silicon film). Carriers released in drain regions can drift or diffuse into the body region and be amplified by parasitic bipolar effects. By heavily doping drain junctions throughout the silicon film, drain strike sensitivity can be significantly reduced. For this case, SEU sensitivity can be limited to gate (body) strikes and by reducing parasitic bipolar effects using body ties, SOI circuits can be fabricated that are very hard to single event effects. These results have important implications on the soft-error reliability of SOI and other oxide-isolated structures, e.g., DRAMs. For SOI SRAMs, it is possible that the additive effects of charge collection by displacement currents and charge released in drain regions may lead to SEU. For trench DRAMs, the retention capacitors are particularly sensitive to charge released in the substrate. Charge collection in retention capacitors by displacement currents can lead to multiple bit upsets (MBUs) in DRAMs, thus significantly degrading the soft-error reliability of DRAMs.

Charge collection by capacitive influence through isolation oxides

This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of present day and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM.

High-speed, high-reliability circuit design for megabit DRAM

Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage supply and a unique word-line driver, reducing stress on short-channel devices. A row and column redundancy technique equivalent to physical disconnect of word lines and bit lines solves leakage problems. Speed enhancements are achieved through bit-line isolation for accelerated column access, a high-speed SRAM-style data path, and by tailoring sensing currents within the limitations of package inductance. The design of a fast 1-Mb DRAM employing these circuits is outlined. >