Abstract
Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage supply and a unique word-line driver, reducing stress on short-channel devices. A row and column redundancy technique equivalent to physical disconnect of word lines and bit lines solves leakage problems. Speed enhancements are achieved through bit-line isolation for accelerated column access, a high-speed SRAM-style data path, and by tailoring sensing currents within the limitations of package inductance. The design of a fast 1-Mb DRAM employing these circuits is outlined. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
