DRAM Node Research Articles

High-numerical aperture extreme ultraviolet scanner for 8-nm lithography and beyond

Current extreme ultraviolet (EUV) projection lithography systems exploit a projection lens with a numerical aperture (NA) of 0.33. It is expected that these will be used in mass production in the 2018/2019 timeframe. By then, the most difficult layers at the 7-nm logic and the mid-10-nm DRAM nodes will be exposed. These systems are a more economical alternative to multiple-exposure by 193 argon fluoride immersion scanners. To enable cost-effective shrink by EUV lithography down to 8-nm half pitch, a considerably larger NA is needed. As a result of the increased NA, the incidence angles of the light rays at the mask increase significantly. Consequently, the shadowing and the variation of the multilayer reflectivity deteriorate the aerial image contrast to unacceptably low values at the current 4× magnification. The only solution to reduce the angular range at the mask is to increase the magnification. Simulations show that the magnification has to be doubled to 8× to overcome the shadowing effects. Assuming that the mask infrastructure will not change the mask form factor, this would inevitably lead to a field size that is a quarter of the field size of the current 0.33-NA step and scan systems and reduce the throughput (TPT) of the high-NA scanner to a value below 100 wafers per hour unless additional measures are taken. This paper presents an anamorphic step and scan system capable of printing fields that are half the field size of the current full field. The anamorphic system has the potential to achieve a TPT in excess of 150 wafers per hour by increasing the transmission of the optics, as well as increasing the acceleration of the wafer stage and mask stage. This makes it an economically viable lithography solution.

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> coupled with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.