DRAM Controller Research Articles

A formal framework to design and prove trustworthy memory controllers

In order to prove conformance to memory standards and bound memory access latency, recently proposed real-time DRAM controllers rely on paper and pencil proofs, which can be troubling: they are difficult to read and review, they are often shown only partially and/or rely on abstractions for the sake of conciseness, and they can easily diverge from the controller implementation, as no formal link is established between both. We propose a new framework written in Coq, in which we model a DRAM controller and its expected behaviour as a formal specification. The trustworthiness in our solution is two-fold: (1) proofs that are typically done on paper and pencil are now done in Coq and thus certified by its kernel, and (2) the reviewer’s job develops into making sure that the formal specification matches the standards—instead of performing a thorough check of the mathematical formalism. Our framework provides a generic DRAM model capturing a set of controller properties as proof obligations, which all implementations must comply with. We focus on properties related to the assertiveness that timing constraints are respected, every incoming request is handled in bounded time, and the DRAM command protocol is respected. We refine our specification with two implementations based on widely-known arbitration policies—First-in First-Out (FIFO) and Time-Division Multiplexing (TDM). We extract proved code from our model and use it as a “trusted core” on a cycle-accurate DRAM simulator.

A Low-power DRAM Controller ASIC with a 36% Reduction in Average Active Power by Increasing On-die Termination Resistance

A low-power DRAM controller ASIC is proposed for point-to-point interconnects such as deep learning applications. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power consumption with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid signal integrity issues. The proposed DRAM controller is implemented in a 65 nm process with an active area of 1.64 mm², 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed controller and a commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the TX current of a clock signal is minimized when the time of flight of the PCB channel is integer multiples of the half period of the clock signal with large TX and RX terminations.

Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin. Because this retention time is over 64,000 times longer than the JEDEC retention-time specification of 0.064 seconds, the DRAM refresh power can be reduced to a negligible level at the data center. To achieve this, the DRAM controller was modified to find weak rows by using three different data patterns at power-on reset and a reserved row of DRAM is used when access to a weak row address occurs during the normal operation.

Sim-D: A SIMD Accelerator for Hard Real-Time Systems

Emerging safety-critical systems require high-performance data-parallel architectures and, problematically, ones that can guarantee tight and safe worst-case execution times. Given the complexity of existing architectures like GPUs, it is unlikely that sufficiently accurate models and algorithms for timing analysis will emerge in the foreseeable future. This motivates our work on Sim-D, a clean-slate approach to designing a real-time data-parallel architecture. Sim-D enforces a predictable execution model by isolating compute- and access resources in hardware. The DRAM controller uninterruptedly transfers tiles of data, requested by entire work-groups. This permits work-groups to be executed as a sequence of deterministic access- and compute phases, scheduling phases from up to two work-groups in parallel. Evaluation using a cycle-accurate timing model shows that Sim-D can achieve performance on par with an embedded-grade NVIDIA TK1 GPU under two conditions: applications refrain from using indirect DRAM transfers into large buffers, and Sim-D's scratchpads provide sufficient bandwidth. Sim-D's design facilitates derivation of safe WCET bounds that are tight within 12.7 percent on average, at an additional average performance penalty of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 9.2 percent caused by scheduling restrictions on phases.

Memory Controller for Vector Processor

To manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase the performance of high-performance application kernels. Adding more vector lanes does not affect the performance, if the processor/memory performance gap dominates. In addition if on/off-chip communication time becomes more critical than computation time, causes performance degradation. The system generates multiple delays due to application’s irregular data arrangement and complex scheduling scheme. Therefore, just like generic scalar processors, all sets of vector machine – vector supercomputers to vector microprocessors – are required to have data management and access units that improve the on/off-chip bandwidth and hide main memory latency. In this work, we propose an Advanced Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized on-chip memory, a memory manager in hardware, and multiple DRAM controllers. We implemented and validated the proposed system on an Altera DE4 FPGA board. The PVMC is also integrated with ARM Cortex-A9 processor on Xilinx Zynq All-Programmable System on Chip architecture. We compare the performance of a system with vector and scalar processors without PVMC. When compared with a baseline vector system, the results show that the PVMC system transfers data sets up to 1.40x to 2.12x faster, achieves between 2.01x to 4.53x of speedup for 10 applications and consumes 2.56 to 4.04 times less energy.

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce ${\rm V}_{\rm min}$ degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3.

Design of write merging and read prefetching buffer in DRAM controller for embedded processor

Write merging and read prefetching are effective methods for improving processor performance, and they are mainly used in processors for desktop or server. As embedded system requires more powerful microprocessor, how to improve the performance of embedded processor is worthy of concern. This paper presents the architecture of write merging and read prefetching buffer in DRAM controller for embedded processor. The evaluation model is constructed, and the result demonstrates that the proposed method can reduce cache miss penalty dramatically. Additionally, the design of DRAM controller with write merging and read prefetching buffer is implemented and verified on FPGA platform, it can reduce CPI by 19.6% on average. Moreover, the RTL module of presented design is synthesized by Design Compiler, and synthesis result shows that hardware cost of proposed architecture is relatively small compared to performance amelioration.

Designing on-chip networks for throughput accelerators

As the number of cores and threads in throughput accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network design. This article explores throughput-effective Network-on-Chips (NoC) for future compute accelerators that employ Bulk-Synchronous Parallel (BSP) programming models such as CUDA and OpenCL. A hardware optimization is “throughput effective” if it improves parallel application-level performance per unit chip area. We evaluate performance of future looking workloads using detailed closed-loop simulations modeling compute nodes, NoC, and the DRAM memory system. We start from a mesh design with bisection bandwidth balanced to off-chip demand. Accelerator workloads tend to demand high off-chip memory bandwidth which results in a many-to-few traffic pattern when coupled with expected technology constraints of slow growth in pins-per-chip. Leveraging these observations we reduce NoC area by proposing a “checkerboard” NoC which alternates between conventional full routers and half routers with limited connectivity. Next, we show that increasing network terminal bandwidth at the nodes connected to DRAM controllers alleviates a significant fraction of the remaining imbalance resulting from the many-to-few traffic pattern. Furthermore, we propose a “double checkerboard inverted” NoC organization which takes advantage of channel slicing to reduce area while maintaining the performance improvements of the aforementioned techniques. This organization also has a simpler routing mechanism and improves average application throughput per unit area by 24.3%.

A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices

This article introduces a 32 nm application processor designed for the latest high-performance smart handheld devices and discusses its design targets and options. To meet unprecedented levels of performance and data throughput demands, this processor employs a 200 MHz-1.6 GHz quad-core CPU, a quad-core GPU, a 2-port interleaving DRAM controller, dedicated video/audio/image processors, a camera/ display controller, and a hierarchical bus. This processor does it in a given power budget and battery life, and also in a given thermal budget by combining 32 nm high-k metal gate process technology with system-level power management techniques and dynamic thermal management techniques.

Topology Aware Task Stealing for On-chip NUMA Multi-core Processors

“The On Chip NUMA Architectures (OCNA) introduce a new challenge namely memory-latency to the scheduling methods. The language run-times and libraries try to explore the processing power of these multiple cores by mapping the user-created tasks on to these cores by using suitable scheduling algorithms with load balancing support to improve throughput. The popular load balancing techniques used are work-sharing and work-stealing and many run-time systems such as Cilk, TBB and wool implement task stealing algorithm to schedule the tasks on to the cores by multiplexing the program generated tasks on to the native worker threads supported by the operating system. But the task stealing strategy applied in present run-time systems assumes the sharing the last level cache (LLC) and common shared bus among all cores on Chip Multi Processor. It tries to optimize the utilization without considering the presence of multiple On Die DRAM controllers and their topological arrangements. Current task stealing technique also suffers from problem of randomly choosing the victim worker queue. In this paper we address these issues and propose a solution for these problems by suggesting few optimizations. Our proposed task stealing strategy dynamically analyzes the topology of the underlying hardware connections and models the group of cores and connections as a logical topology tree. This logical tree is translated into multiple worker pools called stealing domains. By restricting the task stealing within these domains, this strategy is implemented and shows an average of 1.24 times better performance on NAS Parallel Benchmark programs compared to popular runtimes Cilk and OpenMP.

Prefetch-Aware Memory Controllers

Existing DRAM controllers employ rigid, nonadaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetches the same as demand requests, and others always prioritize demands over prefetches. However, none of these rigid policies result in the best performance because they do not take into account the usefulness of prefetches. If prefetches are useless, treating prefetches and demands equally can lead to significant performance loss and extra bandwidth consumption. In contrast, if prefetches are useful, prioritizing demands over prefetches can hurt performance by reducing DRAM throughput and delaying the service of useful requests. This paper proposes a new low hardware cost memory controller, called as Prefetch-Aware DRAM Controller (PADC), that aims to maximize the benefit of useful prefetches and minimize the harm caused by useless prefetches. The key idea is to 1) adaptively prioritize between demands and prefetches, and 2) drop useless prefetches to free up memory system resources, based on prefetch accuracy. Our evaluation shows that PADC significantly outperforms previous memory controllers with rigid prefetch handling policies. Across a wide range of multiprogrammed SPEC CPU 2000/2006 workloads, it improves system performance by 8.2 and 9.9 percent on four and eight-core systems while reducing DRAM bandwidth consumption by 10.7 and 9.4 percent, respectively.

An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration

In an advanced System-on-Chip (SoC) for real-time applications, the arbiter of its on-chip communication subsystem needs to support multiple QoS criteria while providing a hard real-time guarantee. To fulfill both objectives, the arbitration algorithm must dynamically switch between NonReal-Time (NRT) and Real-Time (RT) modes such that use of the RT mode is minimized to best accommodate the overall QoS criteria. In this article, we define a model for this problem, and propose optimal solutions to its associated problems with static and dynamic warning-zone-length assignment. Compared with previous works, the proposed approach enables a bus arbiter to use much less RT mode in providing a Real-Time (RT) guarantee and, therefore, gives the arbiter more opportunity to employ non-RT modes to achieve better overall QoS. Experimental results show that the proposed approach reduces RT mode usage by as much as 37.1%. Moreover, that reduction in RT mode usage helps cut the execution time by 27.0% when applying our approach to an industrial DRAM controller. Another case study on an AMBA-compliant ultra-high-resolution H.264 decoder IP shows that the proposed approach reduces RT mode usage by 26.4%, which leads to an average reduction of 10.4% in decoding time. Finally, when implementing a 16 master arbiter, it costs only 6.9K and 9.5K gates of overhead using the proposed static and dynamic approach, respectively. Therefore, the proposed approach is suitable for real-time SoC applications.

Memory Access Optimized VLSI for 5000-Word Continuous Speech Recognition

We have developed a memory access reduced VLSI chip for 5,000 word speaker-independent continuous speech recognition. This chip employs a context-dependent HMM (hidden Markov model) based speech recognition algorithm, and contains parallel and pipelined hardware units for emission probability computation and Viterbi beam search. To maximize the performance, we adopted several memory access reduction techniques such as sub-vector clustering and multi-block processing for the emission probability computation. We also employed a custom DRAM controller for efficient access of consecutive data. Moreover, we analyzed the access pattern of data to minimize the internal SRAM size while maintaining high performance. The experimental results show that the implemented system performs speech recognition 2.4 and 1.8 times faster than real-time utilizing 32-bit DDR SDRAM and SDR SDRAM, respectively.

DRAM Controller with a Complate Predictor

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

Parallelism-Aware Batch Scheduling

In a chip-multiprocessor (CMP) system, the DRAM system isshared among cores. In a shared DRAM system, requests from athread can not only delay requests from other threads by causingbank/bus/row-buffer conflicts but they can also destroy other threads’DRAM-bank-level parallelism. Requests whose latencies would otherwisehave been overlapped could effectively become serialized. As aresult both fairness and system throughput degrade, and some threadscan starve for long time periods.This paper proposes a fundamentally new approach to designinga shared DRAM controller that provides quality of service to threads,while also improving system throughput. Our parallelism-aware batchscheduler (PAR-BS) design is based on two key ideas. First, PARBSprocesses DRAM requests in batches to provide fairness and toavoid starvation of requests. Second, to optimize system throughput,PAR-BS employs a parallelism-aware DRAM scheduling policythat aims to process requests from a thread in parallel in the DRAMbanks, thereby reducing the memory-related stall-time experienced bythe thread. PAR-BS seamlessly incorporates support for system-levelthread priorities and can provide different service levels, includingpurely opportunistic service, to threads with different priorities.We evaluate the design trade-offs involved in PAR-BS and compareit to four previously proposed DRAM scheduler designs on 4-, 8-, and16-core systems. Our evaluations show that, averaged over 100 4-coreworkloads, PAR-BS improves fairness by 1.11X and system throughputby 8.3% compared to the best previous scheduling technique, Stall-Time Fair Memory (STFM) scheduling. Based on simple request prioritizationrules, PAR-BS is also simpler to implement than STFM.

Design methodology of embedded DRAM with virtual-socket architecture

This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT. On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC. We applied this virtual-socket architecture to the development of the 61-Mb synchronous DRAM core using 0.18-/spl mu/m design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT.

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller

We have developed a 0.25-/spl mu/m, 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscalar datapath that consists of a 32-bit integer unit and a 64-bit single-instruction multiple-data (SIMD) function unit that together have a total of five multiply-adders. An on-chip concurrent Rambus DRAM (C-RDRAM) controller uses interleaved transactions to increase the memory bandwidth of the Rambus channel to 533 Mb/s. The controller also reduces latency by using the transaction interleaving and instruction prefetching. A 64-bit, 200-MHz internal bus transfers data among the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels improve CPU performance because they eliminate a bottleneck in the data supply. The datapath part of this chip was designed using a functional macrocell library that included placement information for leaf cells and resulted in the SIMD function unit of this chip's having 68000 transistors per square millimeter.

Next generation PET data acquisition architectures

New architectures for higher performance data acquisition in PET are proposed. Improvements are demanded primarily by three areas of advancing PET state of the art. First, larger detector arrays such as the Hammersmith ECAT/sup (R/) EXACT HR/sup ++/ exceed the addressing capacity of 32 bit coincidence event words. Second, better scintillators (LSO) make depth-of interaction (DOI) and time-of-flight (TOF) operation more practical. Third, fully optimized single photon attenuation correction requires higher rates of data collection. New technologies which enable the proposed third generation Real Time Sorter (RTS III) include: (1) 80 Mbyte/sec Fibre Channel RAID disk systems, (2) PowerPC on both VMEbus and PCI Local bus, and (3) quadruple interleaved DRAM controller designs. Data acquisition flexibility is enhanced through a wider 64 bit coincidence event word. PET methodology support includes DOI (6 bits), TOF (6 bits), multiple energy windows (6 bits), 512/spl times/512 sinogram indexes (18 bits), and 256 crystal rings (16 bits). Throughput of 10 M events/sec is expected for list-mode data collection as well as both on-line and replay histogramming. Fully efficient list-mode storage for each PET application is provided by real-time bit packing of only the active event word bits. Real-time circuits provide DOI rebinning.

High capacity, high speed histogramming data acquisition memory

A double width CAMAC DRAM store module was developed for use as a histogramming memory in fast time-resolved synchrotron radiation applications to molecular biology. High speed direct memory modify (3 MHz) is accomplished by using a discrete DRAM controller and fast page mode access. The module can be configured using standard SIMMs to sizes of up to 64M-words. The word width is 16 bit and the module can handle overflows by storing the overflow addresses in a dedicated FIFO. Simultaneous front panel DMM/DMI access and CAMAC readout of the overflow addresses is supported.

A delay insensitive approach to the VLSI design of a DRAM controller

The paper presents an application of Delay Insensitive VLSI design to a real case. A Dynamic RAM Controller, matching the specification of the Intel 8202 ® component, has been designed through a delay insensitive methodology, by using a synthesis system developed by the authors. Delay insensitivity is currently a subject of study due to its promising features for VLSI design. Though formal methods have been widely developed, there is a lack of real applications that prove the capabilities of the delay insensitive approach. The main goal of this paper is to show that a delay insensitive methodology is a suitable automated approach to the design of complex VLSI CMOS circuits.