A delay insensitive approach to the VLSI design of a DRAM controller

Abstract

The paper presents an application of Delay Insensitive VLSI design to a real case. A Dynamic RAM Controller, matching the specification of the Intel 8202 ® component, has been designed through a delay insensitive methodology, by using a synthesis system developed by the authors. Delay insensitivity is currently a subject of study due to its promising features for VLSI design. Though formal methods have been widely developed, there is a lack of real applications that prove the capabilities of the delay insensitive approach. The main goal of this paper is to show that a delay insensitive methodology is a suitable automated approach to the design of complex VLSI CMOS circuits.